research-article

TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA

Authors:

Claude Chappert,

Guillaume PrenatAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 2, Issue 2

Article No.: 8, Pages 1 - 19

https://doi.org/10.1145/1534916.1534918

Published: 01 June 2009 Publication History

Abstract

As one of the most promising Spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance, and nonvolatility. The integration of MRAM in FPGAs allows the logic circuit to rapidly configure the algorithm, the routing and logic functions, and easily realize the Runtime Reconfiguration (RTR) and multicontext configuration. However, the conventional MRAM technology based on the Field Induced Magnetic Switching (FIMS) writing approach consumes very high power, large circuit surfaces, and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM’s further development in memory and logic circuit. Thermally Assisted Switching (TAS)-based MRAM is then evaluated to address these issues. In this article, some design techniques, novel computing architecture, and logic components for FPGA logic circuits based on TAS-MRAM technology are presented. By using STMicroelectronics CMOS 90nm technology and a complete TAS-MTJ spice model, some chip characteristic results such as the programming latency (~25ns) and power dissipation (~124pJ) have been calculated or simulated to demonstrate the expected performance of TAS-MRAM-based FPGA logic circuits.

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Cited By

Chandarana PElbtity MF. DeMara RZand R(2024)MRAM-Based FPGAs: A SurveyComputer Memory and Data Storage10.5772/intechopen.108212Online publication date: 10-Jan-2024
https://doi.org/10.5772/intechopen.108212
Barla PJoshi VBhat S(2021)Spintronic devices: a promising alternative to CMOS devicesJournal of Computational Electronics10.1007/s10825-020-01648-6Online publication date: 19-Jan-2021
https://doi.org/10.1007/s10825-020-01648-6
Maciel NMarques ENaviner LZhou YCai H(2019)Magnetic Tunnel Junction ApplicationsSensors10.3390/s2001012120:1(121)Online publication date: 24-Dec-2019
https://doi.org/10.3390/s20010121
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Index Terms

TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA
1. Human-centered computing
  1. Human computer interaction (HCI)

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 2, Issue 2

June 2009

211 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/1534916

Issue’s Table of Contents

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 June 2009

Accepted: 01 November 2008

Revised: 01 October 2008

Received: 01 July 2008

Published in TRETS Volume 2, Issue 2

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Cited By

Chandarana PElbtity MF. DeMara RZand R(2024)MRAM-Based FPGAs: A SurveyComputer Memory and Data Storage10.5772/intechopen.108212Online publication date: 10-Jan-2024
https://doi.org/10.5772/intechopen.108212
Barla PJoshi VBhat S(2021)Spintronic devices: a promising alternative to CMOS devicesJournal of Computational Electronics10.1007/s10825-020-01648-6Online publication date: 19-Jan-2021
https://doi.org/10.1007/s10825-020-01648-6
Maciel NMarques ENaviner LZhou YCai H(2019)Magnetic Tunnel Junction ApplicationsSensors10.3390/s2001012120:1(121)Online publication date: 24-Dec-2019
https://doi.org/10.3390/s20010121
Yoon Bae GHwang YLee SKim TPark W(2019)Reconfigurable logic for carry-out computing in 1-bit full adder using a single magnetic tunnel junctionSolid-State Electronics10.1016/j.sse.2019.02.001Online publication date: Mar-2019
https://doi.org/10.1016/j.sse.2019.02.001
Huang KZhao RLian Y(2018)Racetrack Memory-Based Nonvolatile Storage Elements for Multicontext FPGAsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.247470624:5(1885-1894)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2015.2474706
Yuan ZLiu YLi JHu JXue CYang H(2017)CP-FPGA: Energy-Efficient Nonvolatile FPGA With Offline/Online Checkpointing OptimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.268046425:7(2153-2163)Online publication date: Jul-2017
https://doi.org/10.1109/TVLSI.2017.2680464
Zand RRoohi ASalehi SDeMara R(2016)Scalable Adaptive Spintronic Reconfigurable Logic Using Area-Matched MTJ DesignIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2016.253209963:7(678-682)Online publication date: Jul-2016
https://doi.org/10.1109/TCSII.2016.2532099
Xue YCronin PYang CHu J(2016)Routing path reuse maximization for efficient NV-FPGA reconfiguration2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2016.7428038(360-365)Online publication date: Jan-2016
https://doi.org/10.1109/ASPDAC.2016.7428038
Kang WZhang YWang ZKlein JChappert CRavelosona DWang GZhang YZhao W(2015)SpintronicsACM Journal on Emerging Technologies in Computing Systems10.1145/266335112:2(1-42)Online publication date: 2-Sep-2015
https://dl.acm.org/doi/10.1145/2663351
Rajaei RFazeli MTabandeh M(2015)Soft Error-Tolerant Design of MRAM-Based Nonvolatile Latches for Sequential LogicsIEEE Transactions on Magnetics10.1109/TMAG.2014.237527351:6(1-14)Online publication date: Jun-2015
https://doi.org/10.1109/TMAG.2014.2375273
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