research-article

An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures

Authors:

Gabriel M. Silberman,

Kemal EbciogluAuthors Info & Claims

Computer, Volume 26, Issue 6

Pages 39 - 56

https://doi.org/10.1109/2.214441

Published: 01 June 1993 Publication History

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Abstract

An architectural framework that allows software applications and operating system code written for a given instruction set to migrate to different, higher performance architectures is described. The framework provides a hardware mechanism that enhances application performance while keeping the same program behavior from a user perspective. The framework is designed to accommodate program exceptions, self-modifying code, tracing, and debugging. Examples are given for IBM System/390 operating-system code and AIX utilities, showing the performance potential of the scheme using a very long instruction word (VLIW) machine as the high-performance target architecture.

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Caballero JLin Z(2016)Type Inference on ExecutablesACM Computing Surveys10.1145/289649948:4(1-35)Online publication date: 2-May-2016
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Kültürsay EEbcioğlu KKüçük GKandemir M(2016)Memory Partitioning in the LimitInternational Journal of Parallel Programming10.1007/s10766-015-0380-744:2(337-380)Online publication date: 1-Apr-2016
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Kim HSmith J(2003)Hardware Support for Control Transfers in Code CachesProceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture10.5555/956417.956565Online publication date: 3-Dec-2003
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Computer Volume 26, Issue 6

June 1993

113 pages

ISSN:0018-9162

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 June 1993

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Caballero JLin Z(2016)Type Inference on ExecutablesACM Computing Surveys10.1145/289649948:4(1-35)Online publication date: 2-May-2016
https://dl.acm.org/doi/10.1145/2896499
Kültürsay EEbcioğlu KKüçük GKandemir M(2016)Memory Partitioning in the LimitInternational Journal of Parallel Programming10.1007/s10766-015-0380-744:2(337-380)Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1007/s10766-015-0380-7
Kim HSmith J(2003)Hardware Support for Control Transfers in Code CachesProceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture10.5555/956417.956565Online publication date: 3-Dec-2003
https://dl.acm.org/doi/10.5555/956417.956565
Dehnert JGrant BBanning JJohnson RKistler TKlaiber AMattson JJohnson RConte THwu W(2003)The Transmeta Code Morphing™ SoftwareProceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization10.5555/776261.776263(15-24)Online publication date: 23-Mar-2003
https://dl.acm.org/doi/10.5555/776261.776263
Gschwind MEbcioğlu KAltman ESathaye SReynders JVeidenbaum A(2000)Binary translation and architecture convergence issues for IBM system/390Proceedings of the 14th international conference on Supercomputing10.1145/335231.335264(336-347)Online publication date: 8-May-2000
https://dl.acm.org/doi/10.1145/335231.335264
Conte TSathaye S(2000)Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation CompatibilityIEEE Transactions on Computers10.1109/12.86802749:8(814-825)Online publication date: 1-Aug-2000
https://dl.acm.org/doi/10.1109/12.868027
Ebcioglu KAltman ESathaye SGschwind M(1999)Execution-Based Scheduling for VLIW ArchitecturesProceedings of the 5th International Euro-Par Conference on Parallel Processing10.5555/646664.700739(1269-1280)Online publication date: 31-Aug-1999
https://dl.acm.org/doi/10.5555/646664.700739
Ebcioğlu KAltman EGschwind MSathaye SRonen RFarrens MSpillinger I(1999)Optimizations and oracle parallelism with dynamic translationProceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture10.5555/320080.320124(284-295)Online publication date: 16-Nov-1999
https://dl.acm.org/doi/10.5555/320080.320124
Rau BKathail VAditya S(1999)Machine-Description Driven Compilers for EPIC and VLIW ProcessorsDesign Automation for Embedded Systems10.1023/A:10088425218054:2-3(71-118)Online publication date: 1-Mar-1999
https://dl.acm.org/doi/10.1023/A%3A1008842521805
Park SShim SMoon SSmotherman MConte T(1997)Evaluation of scheduling techniques on a SPARC-based VLIW testbedProceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture10.5555/266800.266811(104-113)Online publication date: 1-Dec-1997
https://dl.acm.org/doi/10.5555/266800.266811
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Increasing the instruction fetch rate via block-structured instruction set architectures

Block enlargement optimizations for increasing the instruction fetch rate in block-structured instruction set architectures

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