Nothing Special   »   [go: up one dir, main page]

skip to main content
research-article

Driver modeling and alignment for worst-case delay noise

Published: 01 April 2003 Publication History

Abstract

In this paper, we present a new approach to model the impact of cross-coupling noise on interconnect delay. We introduce a new linear driver model that accurately models the noise pulse induced on a switching signal net due to cross-coupling capacitance. The proposed model effectively captures the nonlinear behavior of the victim-driver gate during its transition and has an average error below 8% whereas the traditional approach using a Thevenin model incurs an average error of 48%. The proposed linear driver model enables the use of linear superposition which allows the analysis of large interconnects and an efficient determination of the worst-case transition times of the aggressor nets. We proposed a new approach to determine the worst-case alignment of the aggressor net transitions with respect to the victim net transition, emphasizing the need to maximize not merely the delay of the interconnect alone but the combined delay of the interconnect and receiver gate. We show that in the presence of multiple aggressor nets, the worst case delay may occur when their noise peaks are not aligned, although the error incurred from aligning all peaks is small in practice. We then show that the worst-case alignment time of the combined noise pulse from all aggressors with respect to the victim transition is a nonlinear function of the receiver gate output loading, the victim transition time, and the noise pulsewidth and height. To efficiently compute the worst-case alignment time, we propose a new representation of the alignment such that it closely fits a linear function of the input variables. The worst-case alignment time is then computed for a gate using a precharacterization approach, requiring only eight sample points while maintaining a small error. The proposed methods were implemented in an industrial noise analysis tool called ClariNet. Results on industrial designs, including a large PPCmicroprocessor design, are presented to demonstrate the effectiveness of our approach.

References

[1]
{1} G. Yee, R. Chandra, V. Ganesan, and C. Sechen, "Wire delay in the presence of crosstalk," in Proc. TAU, 1997, pp. 170-175.
[2]
{2} D. Sylvester and K. Keutzer, "Getting to the bottom of deep submicron," in Proc. Int. Conf. Comput.-Aided Design, Nov. 1998, pp. 203-211.
[3]
{3} J. M. Zurada, Y. S. Joo, and S. V. Bell, "Dynamic noise margins of MOS logic gates," Proc. IEEE ISCAS, pp. 1153-1156, 1989.
[4]
{4} K. L. Shepard, V. Narayanan, P. C. Elemendorf, and G. Zheng, "Global harmony: Coupled noise analysis for full-chip RC interconnect networks," in Proc. Int. Conf. Comput.-Aided Design, 1997, pp. 139-146.
[5]
{5} K. L. Shepard, "Design methodologies for noise in digital integrated circuits," Proc. ACM/IEEE Design Automation Conf., pp. 94-99, 1998.
[6]
{6} R. Levy, D. Blaauw, G. Braca, A. Dasgupta, A. Grinshpon, C. Oh, B. Orshav, S. Sirichotiyakul, and V. Zolotov, "Clarinet: A noise analysis tool for deep submicron design," Proc. IEEE/ACM Design Automat. Conf., pp. 233-238, June 2000.
[7]
{7} M. Becer and I. J. Hajj, "An analytical model for delay and crosstalk estimation with application to decoupling," Proc. IEEE Int. Symp. Quality Electron. Design, pp. 51-57, 2000.
[8]
{8} A. B. Kahng, S. Muddu, and D. Vidhani, "Noise and delay uncertainty studies for coupled RC interconnects," in Proc. ASIC/SOC Conf., 1999, pp. 3-8.
[9]
{9} T. Xue, E. S. Kuh, and D. Wang, "Post global routing crosstalk risk estimation and reduction," Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, pp. 616-619, 1994.
[10]
{10} T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Trans. Electron Devices, vol. 40, pp. 118-124, Jan. 1993.
[11]
{11} A. Vittal, L. H. Chen, M. Marek-Sadowska, K.-P. Wang, and S. Yang, "Crosstalk in VLSI interconnections," IEEE Trans. Comput.-Aided Design Integrat. Circuits Syst., vol. 18, no. 12, pp. 1817-1824, Dec. 1999.
[12]
{12} A. Devgan, "Efficient coupled noise estimation for on-chip interconnects," Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, pp. 147-153. 1997.
[13]
{13} M. Kuhlmann, S. S. Sapatnekar, and K. K. Parhi, "Efficient crosstalk estimation," in Proc. Int. Conf Comput. Design, 1999, pp. 266-272.
[14]
{14} C. J. Alpert, A. Devgan, and S. T. Quay, "'Buffer insertion for noise and delay optimization," in Proc. Design Automat. Conf., 1998, pp. 362-367.
[15]
{15} M. R. Becer, D. Blaauw, S. Sirichotiyakul, R. Levy, C. Oh, V. Zolotov, I. Zuo, and I. J. Hajj, "A global driver sizing tool for functional crosstalk noise avoidance," Proceedings IEEE Int. Symp. Quality Electron. Design, pp. 158-163, 2001.
[16]
{16} T. STohr, H. Alt, A. Hetzel, and K. Koehl, "Analysis, reduction and avoidance of crosstalk on VLSI chips," in Proc. Int. Symp. Physical Design, 1998, pp. 211-218.
[17]
{17} A. Vittal and M. Marek-Sadowska, "Crosstalk reduction for VLSI" IEEE Trans. Comput.-Aided Design, vol. 16, pp. 290-298, Mar. 1997.
[18]
{18} H. Zhou and D. F. Wong, "Global routing with crosstalk contraints" Proc. IEEE/ACM Design Automat. Conf., pp. 374-377, 1998.
[19]
{19} D. A. Kirkpatrick and A. L. Sangiovanni-Vincentelli, "Techniques for crosstalk avoidance in the physical design of high-performance digital systems," Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, pp. 616-619, 1994.
[20]
{20} A. B. Kahng, S. Muddu, and E. Sarto, "On switching factor based anaysis of coupled RC interconnects," Proc. IEEE/ACM Design Automat. Conf., pp. 79-84, 2000.
[21]
{21} A. Odabasioglu, M. Celik, and L. T. Pileggi, "PRIMA: Passive reduced-order interconnect macromodeling algorithm," in Proc. Int. Conf. Comput.-Aided Design, 1997, pp. 58-65.
[22]
{21} D. Blaauw, A. Dharchoudhurry, and A. Devgan, "Signal integrity in high performance design," in Tutorial Presentation, IEEE/ACM Int. Conf. Comput.-Aided Design, 1999.
[23]
{23} F. Dartu, N. Menezes, and L. T. Pileggi, "Performance computation for precharacterized CMOS gates with RC loads," IEEE Trans. Comput.- Aided Design of Integrat. Circuits Syst., vol. 15, no. 5, pp. 544-553, May 1996.
[24]
{24} J. Qian, S. Pullela, and L. T. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Trans. Comput.-Aided Design, pp. 1526-1555, Dec. 1994.
[25]
{25} F. Dartu and L. T. Pileggi, "Calculating worst-case gate delays due to dominant capacitance coupling," in Proc. DAC, June 1997, pp. 46-51.
[26]
{26} P. D. Gross, R. Arunachalam, K. Rajagopal, and L. T. Pileggi, "Determination of worst-case aggressor alignment for delay calculation," Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, pp. 212-219, Nov. 1998.
[27]
{27} S. Sapatnekar, "Capturing the effect of crosstalk on delay," in Proc. VLSI Design 2000, Jan. 2000, pp. 364-369.
[28]
{28} R. Arunachalam, K. Rajagopal, and L. T. Pileggi, "TACO: Timing analysis with coupling," in Proc. Design Automat. Conf., June 2000, pp. 266-269.
[29]
{29} P. Chen, D. A. Kirkpatrick, and K. Keutzer, "Switching window computation for static timing analysis in the presence of crosstalk noise," Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, pp. 331-337, 2000.
[30]
{30} Y. Sasaki and G. De Micheli, "Crosstalk delay analysis using relative window method," in IEEE Int. ASIC/SOC Conf., 1999, pp. 9-13.
[31]
{31} P. Chen and K. Keutzer, "Toward true crosstalk noise analysis," Proc. IEEE/ACM Design Automat. Conf., 1999.
[32]
{32} L. H. Chen and M. Marek-Sadowska, "Aggressor alignment for worst-case crosstalk noise," IEEE Trans. Comput.-Aided Design, vol. 20, pp. 612-621, May 2001.

Cited By

View all
  • (2020)Misalignment-aware energy modeling of narrow buses for data encoding schemesIntegration, the VLSI Journal10.1016/j.vlsi.2020.01.00172:C(58-65)Online publication date: 29-Jun-2020
  • (2009)Worst-case aggressor-victim alignment with current-source driver modelsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629919(13-18)Online publication date: 26-Jul-2009
  • (2008)A "true" electrical cell model for timing, noise, and power grid verificationProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391589(462-467)Online publication date: 8-Jun-2008
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 11, Issue 2
April 2003
143 pages

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 April 2003

Author Tags

  1. cross-coupled noise analysis
  2. delay computation
  3. delay noise
  4. signal integrity
  5. timing verification

Qualifiers

  • Research-article

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 21 Sep 2024

Other Metrics

Citations

Cited By

View all
  • (2020)Misalignment-aware energy modeling of narrow buses for data encoding schemesIntegration, the VLSI Journal10.1016/j.vlsi.2020.01.00172:C(58-65)Online publication date: 29-Jun-2020
  • (2009)Worst-case aggressor-victim alignment with current-source driver modelsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629919(13-18)Online publication date: 26-Jul-2009
  • (2008)A "true" electrical cell model for timing, noise, and power grid verificationProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391589(462-467)Online publication date: 8-Jun-2008
  • (2007)A nonlinear cell macromodel for digital applicationsProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326217(678-685)Online publication date: 5-Nov-2007
  • (2007)Top-k aggressors sets in delay noise analysisProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278523(174-179)Online publication date: 4-Jun-2007
  • (2007)Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.90410015:11(1205-1214)Online publication date: 1-Nov-2007
  • (2006)A multi-port current source model for multiple-input switching effects in CMOS library cellsProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1146974(247-252)Online publication date: 24-Jul-2006
  • (2006)Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback LoopProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.67(153-159)Online publication date: 27-Mar-2006
  • (2005)Statistical modeling of cross-coupling effects in VLSI interconnectsProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120922(503-506)Online publication date: 18-Jan-2005
  • (2005)An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing AnalysisProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.16(654-661)Online publication date: 21-Mar-2005

View Options

View options

Get Access

Login options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media