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An O(bn2) time algorithm for optimal buffer insertion with b buffer types

Published: 01 November 2006 Publication History

Abstract

Buffer insertion is a popular technique to reduce the interconnect delay. The classic buffer insertion algorithm of van Ginneken has a time complexity of O(n2), where n is the number of buffer positions. Lillis, Cheng, and Lin extended van Ginneken's algorithm to allow b buffer types in O(b2n2) time. For modern design libraries that contain hundreds of buffers, it is a serious challenge to balance the speed and performance of the buffer insertion algorithm. In this paper, we present a new algorithm that computes the optimal buffer insertion in O(bn2) time. The reduction is achieved by the observation that the (Q,C) pairs of the candidates that generate the new candidates must form a convex hull. On industrial test cases, the new algorithm is faster than the previous best buffer insertion algorithms by orders of magnitude. Since van Ginneken's algorithm with multiple buffer types are used by most existing algorithms on buffer insertion and buffer sizing, our new algorithm improves the performance of all these algorithms.

Cited By

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  • (2012)Guiding a physical design closure system to produce easier-to-route designs with more predictable timingProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228442(465-470)Online publication date: 3-Jun-2012
  • (2009)A faster approximation scheme for timing driven minimum cost layer assignmentProceedings of the 2009 international symposium on Physical design10.1145/1514932.1514969(167-174)Online publication date: 29-Mar-2009
  • (2009)Fast buffering for optimizing worst slack and resource consumption in repeater treesProceedings of the 2009 international symposium on Physical design10.1145/1514932.1514942(43-50)Online publication date: 29-Mar-2009
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Information & Contributors

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Published In

cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 25, Issue 3
November 2006
219 pages

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IEEE Press

Publication History

Published: 01 November 2006

Author Tags

  1. Buffer insertion
  2. Elmore delay
  3. data structure
  4. interconnect
  5. routing

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Cited By

View all
  • (2012)Guiding a physical design closure system to produce easier-to-route designs with more predictable timingProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228442(465-470)Online publication date: 3-Jun-2012
  • (2009)A faster approximation scheme for timing driven minimum cost layer assignmentProceedings of the 2009 international symposium on Physical design10.1145/1514932.1514969(167-174)Online publication date: 29-Mar-2009
  • (2009)Fast buffering for optimizing worst slack and resource consumption in repeater treesProceedings of the 2009 international symposium on Physical design10.1145/1514932.1514942(43-50)Online publication date: 29-Mar-2009
  • (2008)A polynomial time approximation scheme for timing constrained minimum cost layer assignmentProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509491(112-115)Online publication date: 10-Nov-2008

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