Cited By
View all- Namba KLombardi F(2016)Single Multiscale-Symbol Error Correction Codes for Multiscale Storage SystemsIEEE Transactions on Computers10.1109/TC.2015.245602465:6(2005-2009)Online publication date: 6-May-2016
Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM)
Pages 2092 - 2097
Abstract
This manuscript proposes non-binary orthogonal Latin square (OLS) codes that are amenable to a multilevel phase change memory (PCM). This is based on the property that the proposed (n symbols, ksymbols) t-symbol error correcting code uses the same H matrix as an (n bits, kbits) binary t-bit error correcting OLS code. The new codes are shown to have a shorter check bit length and better probability in encoding/decoding than conventional binary OLS codes. Extensive results are provided for assessment and comparison. The proposed codes are also shown to be always better than the matrix codes, i.e. independently of the metric and the parameters employed in the comparison.
References
[1]
N. Papandreou, A. Pantazi, A. Sebastian, M. Breitwisch, C. Lam, H. Pozidis, and E. Eleftheriou, “Multilevel phase-change memory,” in Proc. IEEE Int. Conf. Electron. Circuits Syst., 2010, pp. 1017–1020 .
[2]
X. Q. Wei, L. P. Shi, R. Walia, T. C. Chong, R. Zhao, X. S. Miao, and B. S. Quek, “HSPICE macromodel of PCRAM for binary and multilevel storage,” IEEE Trans. Electron. Dev., vol. 53, no. 1, pp. 56 –62, Jan. 2006.
[3]
R. A. Cobley and C. D. Wright, “Parameterized SPICE model for a phase-change RAM device,” IEEE Trans. Electron. Dev., vol. 53, no. 1, pp. 112–118, Jan. 2006.
[4]
D. Ielmini, A. L. Lacaita, and D. Mantegazza, “ Recovery and drift dynamics of resistance and threshold voltages in phase-change memories,” IEEE Trans. Electron. Dev., vol. 54, no. 2, pp. 308–315, Feb. 2007.
[5]
S. Kim, B. Lee, M. Asheghi, F. Hurkx, J. P. Reifenberg, K. E. Goodson, and H. S. P. Wong, “Resistance and threshold switching voltage drift behavior in phase-change memory and their temperature dependence at microsecond time scales studied using a micro-thermal stage,” IEEE Trans. Electron. Dev., vol. 58, no. 3, pp. 584 –592, Mar. 2011.
[6]
I. V. Karpov, M. Mitra, D. Kau, G. Spadini, Y. A. Kryukov, and V. G. Karpov, “Fundamental drift of parameters in chalcogenide phase change memory,” J. Appl. Phys., vol. 102, no. 12, pp. 124503, Dec. 2007.
[7]
S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall, 2004.
[8]
R. Datta and N. A. Touba, “Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories,” in Proc. IEEE VLSI Test Symp., 2011, pp. 134–139.
[9]
H. Y. Hsiao, D. C. Bossen, and R. T. Chien, “Orthogonal Latin square codes,” IBM J. Res. Dev., vol. 14, no. 4, pp. 390–394, Jul. 1970.
[10]
B. Rajendran, R. W. Cheek, L. A. Lastras, M. M. Franceschini, M. J. Breitwisch, A. G. Schrott, J. Li, R. K. Montoye, L. Chang, and C. Lam, “Demonstration of CAM and TCAM using phase change devices,” in Proc. IEEE Int. Memory Workshop, 2011, pp. 1–4.
[11]
C. Argyrides, F. D. K. Pradhan, and T. Kocak, “ Matrix codes for reliable and cost efficient memory chips,” IEEE Trans. Very Large Scale Integr. Syst., vol. 19, no. 3, pp. 420–428, Mar. 2011.
[12]
P. Reviriego, C. Argyrides, J. A. Maestro, and D. K. Pradhan, “Improving memory reliability against soft errors using block parity,” IEEE Trans. Nucl. Sci., vol. 58, no. 3, pp. 981 –986, Jun. 2011.
[13]
M. Boniardi, D. Ielmini, S. Lavizzari, A. L. Lacaita, A. Redaelli, and A. Pirovano, “Statistical and scaling behavior of structural relaxation effects in phase-change memory (PCM) devices,” in Proc. IEEE Int. Rel. Phys. Symp., 2009, pp. 122–127.
[14]
W. Xu and T. Zhang “A time-aware fault tolerance scheme to improve reliability of multilevel phase-change memory in the presence of significant resistance drift,” IEEE Trans. Very Large Scale Integr. Syst., vol. 19, no. 8, pp. 1357–1367, Aug. 2011.
[15]
P. Junsangsri, J. Han, and F. Lombardi, “Macromodeling a phase change memory (PCM) cell by HSPICE,” in Proc. IEEE/ACM Int’l Symp. Nanoscale Archit., 2012, pp. 77–84.
[16]
E. Fujiwara, K. Namba, and M. Kitakami, “Parallel Decoding for Burst Error Control Codes,” in Proc. IEEE Int. Symp. Inf. Theory, 2002, p. 429.
[17]
C.-Y. Chen, Q. Huang, C.-C. Chao, and S. Lin, “Two low-complexity reliability-based message-passing algorithms for decoding non-binary LDPC codes,” IEEE Trans. Commun., vol. 58, no. 11, pp. 3140–3147, Nov. 2010.
[18]
Z. Chishti, A. R. Alameldeen, C. Wilkerson, W. Wu, and S.-L. Lu, “Improving cache lifetime reliability at ultra-low voltages,” in Proc. Annu. IEEE/ACM Int. Symp. Microarchit, 2009, pp. 89–99.
[19]
C. J. Colbourn and J. H. Dinitz, The CRC Handbook of Combinatorial Designs. Boca Raton, FL, USA: CRC Press, 1996.
[20]
E. Fujiwara, Code Design for Dependable Systems: Theory and Practical Applications. New York, NY, USA: Wiley-Interscience, 2006 .
Index Terms
- Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM)
Index terms have been assigned to the content through auto-classification.
Recommendations
A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes
Radiation-induced soft errors are a major reliability concern for memories. To ensure that memory contents are not corrupted, single error correction double error detection (SEC-DED) codes are commonly used, however, in advanced technology nodes, soft ...
Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes
In recent years, there has been a growing interest in multi-bit error correction codes (ECCs) to protect SRAM memories. This has been caused by the increased number of multiple errors that memories suffer as technology scales. To be suitable to protect ...
Write reconstruction for write throughput improvement on MLC PCM based main memory
The emerging Phase Change Memory (PCM) is considered as one of the most promising candidates to replace DRAM as main memory due to its better scalability and non-volatility. With multi-bit storage capability, Multiple-Level-Cell (MLC) PCM outperforms ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
Copyright © 2014.
Publisher
IEEE Computer Society
United States
Publication History
Published: 01 July 2015
Author Tags
Qualifiers
- Research-article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- View Citations1Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 22 Sep 2024
Other Metrics
Citations
Cited By
View all- Namba KLombardi F(2016)Single Multiscale-Symbol Error Correction Codes for Multiscale Storage SystemsIEEE Transactions on Computers10.1109/TC.2015.245602465:6(2005-2009)Online publication date: 6-May-2016
View Options
View options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in