research-article

Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process

Authors:

Kodai Yamada,

Haruki Maruoka,

Jun Furuta,

Kazutoshi KobayashiAuthors Info & Claims

2018 IEEE International Reliability Physics Symposium (IRPS)

Pages P-SE.3-1 - P-SE.3-5

https://doi.org/10.1109/IRPS.2018.8353691

Published: 11 March 2018 Publication History

Abstract

Three different latch structures are fabricated in a 65 nm FDSOI process. We evaluate soft-error tolerance of latches by device simulations and a particle, neutron, heavy-ion irradiation tests in order to identify which transistor type is dominant to cause soft errors. The latch structure including an inverter with stacked NMOS and unstacked PMOS transistors has enough tolerance against soft errors by up to heavy ions with 40 MeV-cm<sup>2</sup>/mg. It suggests that soft error rates are dominant on NMOS transistors not only in terrestrial regions but also in outer space.

References

[1]

P. Hazucha, T. Karnik, J. Maiz, S. Wal-STRA, B. Bloechel, J. Tschanz, G. Dermer, S. Hareland, P. Armstro ng, and S. Borkar. Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25 μm to 90-nm generation. In IEEE Int. Electron Devices Meeting, pages 523–526, 2003.

Google Scholar

[2]

K. Castellani-Coulie, B. Sagnes, F. Saigne, J. M. Palau, M. C. Calvet, P. E. Dodd, and F. W. Sexton. Comparison of nmos and pmos transistor sensitivity to seu in srams by device simulation. IEEE Trans. Nucl. Sci., 50(6): 2239–2244, Dec 2003.

Google Scholar

[3]

S. Jagannathan, M. J. Gadlage, B. L. Bhuva, R. D. Schrimpf, B. Narasimham, J. Chetia, J. R. Ahlbin, and L. W. Massengill. Independent measurement of set pulse widths from n-hits and p-hits in 65-nm cmos. IEEE Trans. Nucl. Sci., 57(6): 3386–3391, Dec 2010.

Google Scholar

[4]

P. Roche, J.-L. Autran, G. Gasiot, and D. Munteanu. Technology downscaling worsening radiation effects in bulk: SOI to the rescue. In IEEE Int. Electron Devices Meeting, pages 31.1.1–31.1.4, Dec. 2013.

Google Scholar

[5]

A. Makihara, M. Midorikawa, T. Yamaguchi, Y. Iide, T. Yokose, Y. Tsuchiya, T. Arimitsu, H. Asai, H. Shindou, S. Kuboyama, and S. Matsuda. Hardness-by-design approach for 0.15 um fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity. IEEE Trans. Nucl. Sci.. 52(6): 2524–2530. Dec. 2005.

Google Scholar

[6]

N. Sugii, R. Tsuchiya, T. Ishigaki, Y. Morita, H. Yoshimoto, and S. Kimura. Local Vth variability and scalability in silicon-on-thin-box (SOTB) CMOS with small random-dopant fluctuation. Trans Electron Devices, 57(4): 835–845, April. 2010.

Google Scholar

[7]

H. Maruoka, M. Hifumi, J. Furuta, and K. Kobayashi. A non-redundant low-power flip flop with stacked transistors in a 65 nm thin BOX FDSOI process. In 2016 16th European Conf. on Radiation and Its Effects on Components and Syst., pages 1–4, Sept 2016.

Google Scholar

[8]

K. Yamada, H Maruoka, J. Furuta, and K. Kobayashi. Radiation-hardened flip-flops with low-delay overheads using PMOS pass-transistors to suppress a set pulse in a 65 nm FDSOI process. In The Conf. Radiation and Its Effects on Components and Syst., Oct. 2017.

Google Scholar

[9]

C. W. Slayman. Theoretical correlation of broad spectrum neutron sources for accelerated soft error testing. IEEE Trans. Electron Devices, 57(6): 3163–3168, December 2010.

Google Scholar

[10]

J. S. Kauppila, T. D. Loveless, R. C. Quinn, J. A. Maharrey, M. L. Alles, M. W. McCurdy, R. A. Reed, B. L. Bhuva, L. W. Massengill, and K. Lilja. Utilizing device stacking for area efficient hardened soi flip-flop designs. In IEEE Int. Rel. Physics Symp (IRPS), pages SE.4.1–SE.4.7, June. 2014.

Google Scholar

[11]

M. A. Xapsos, C. Stauffer, T. Jordan, J. L. Barth, and R. A. Mewaldt. Model for cumulative solar heavy ion energy and linear energy transfer spectra. IEEE Trans. Nucl. Sci., 54(6): 1985–1989, Dec. 2007.

Google Scholar

[12]

H. Asai, K. Sugimoto, I. Nashiyama, Y. Iide, K. Shiba, M. Matsuda, and Y. Miyazaki. Terrestrial neutron-induced single-event burnout in SiC power diodes. IEEE Trans. Nucl. Sci., 59(4): 880–885, Aug 2012.

Google Scholar

Cited By

View all

Resch SKhatamifard SChowdhury ZZabihi MZhao ZCilasun HWang JSapatnekar SKarpuzcu U(2022)Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating ConditionsACM Transactions on Embedded Computing Systems10.1145/352013021:5(1-36)Online publication date: 9-Dec-2022
https://dl.acm.org/doi/10.1145/3520130

Index Terms

Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process
1. Hardware
  1. Hardware test
  2. Robustness

Index terms have been assigned to the content through auto-classification.

Recommendations

Channel hot-carrier degradation in pMOS and nMOS short channel transistors with high-k dielectric stack

A comparison between pMOS and nMOS short channel transistors with high-k dielectric subjected to channel hot-carrier (CHC) stress is presented. Smaller CHC degradation is observed in pMOS devices. At high temperature, the CHC degradation increases for ...
Numerical simulation of random dopant fluctuation in sub-65 nm metal-oxide-semiconductor field effect transistors
MATH'05: Proceedings of the 8th WSEAS International Conference on Applied Mathematics

As the gate length of MOSFET devices shrinks down below 100 nm, the fluctuation of major devices parameter, namely, threshold voltage (V_TH), subthreshold swing, drain current (I_D) and subthreshold leakage current due to influences of processes ...
PMOS-only sleep switch dual-threshold voltage domino logic in sub-65-nm CMOS technologies

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

2018 IEEE International Reliability Physics Symposium (IRPS)

Mar 2018

15 pages

Publisher

IEEE Press

Publication History

Published: 11 March 2018

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 27 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Resch SKhatamifard SChowdhury ZZabihi MZhao ZCilasun HWang JSapatnekar SKarpuzcu U(2022)Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating ConditionsACM Transactions on Embedded Computing Systems10.1145/352013021:5(1-36)Online publication date: 9-Dec-2022
https://dl.acm.org/doi/10.1145/3520130

View Options

View options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Abstract

References

Cited By

Index Terms

Recommendations

Channel hot-carrier degradation in pMOS and nMOS short channel transistors with high-k dielectric stack

Numerical simulation of random dopant fluctuation in sub-65 nm metal-oxide-semiconductor field effect transistors

PMOS-only sleep switch dual-threshold voltage domino logic in sub-65-nm CMOS technologies

Comments

Information

Published In

Publisher

Publication History

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Login options

Full Access

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations