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PADS: A Pattern-Driven Stencil Compiler-Based Tool for Reuse of Optimizations on GPGPUs

Published: 07 December 2011 Publication History

Abstract

Stencil computations are core of wide range of scientific and engineering applications. A lot of efforts have been put into improving efficiency of stencil calculations on different platforms, but unfortunately it is not easy to reuse. In this paper we present a PAttern-Driven Stencil compiler-based tool and a simple tuning system to reuse those well optimized methods and codes. We also suggest extensions to OpenMP, depicting high-level data structures in order to facilitate recognition of various stencil computation patterns. The PADS allows programmers to rewrite kernel of stencils or reuse source-to-source translator outputs as optimized stencil template codes with related tuning parameters, In addition, PADS consists of a OpenMP to CUDA translator and code generator using optimized template codes. It also obtains architecture-specific parameters to tune stencils across different GPU platforms. To demonstrate our system flexibility and performance portability, we illustrate four different stencil computations, Laplacian operator with Jacobi iterative method, divergence operator, 3 dimension 25 point stencil and a 2D heat equation using ADI method with periodic boundary conditions. PADS succeeds in generating all these four stencil codes using different optimization strategies and delivers a promising performance improvement.

Cited By

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  • (2018)Optimizing inter-nest data locality in imperfect stencils based on loop blockingThe Journal of Supercomputing10.5555/3288339.328836574:10(5432-5460)Online publication date: 1-Oct-2018
  • (2015)SDSLcProceedings of the 5th International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing10.1145/2830018.2830025(1-10)Online publication date: 15-Nov-2015
  • (2014)Trace-Driven Memory Access Pattern Recognition in Computational KernelsProceedings of the Second Workshop on Optimizing Stencil Computations10.1145/2686745.2686748(25-32)Online publication date: 20-Oct-2014
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Information

Published In

cover image Guide Proceedings
ICPADS '11: Proceedings of the 2011 IEEE 17th International Conference on Parallel and Distributed Systems
December 2011
1069 pages
ISBN:9780769545769

Publisher

IEEE Computer Society

United States

Publication History

Published: 07 December 2011

Author Tags

  1. GPGPU
  2. OpenMP
  3. optimization reuse
  4. pattern matching
  5. stencil computation

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Cited By

View all
  • (2018)Optimizing inter-nest data locality in imperfect stencils based on loop blockingThe Journal of Supercomputing10.5555/3288339.328836574:10(5432-5460)Online publication date: 1-Oct-2018
  • (2015)SDSLcProceedings of the 5th International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing10.1145/2830018.2830025(1-10)Online publication date: 15-Nov-2015
  • (2014)Trace-Driven Memory Access Pattern Recognition in Computational KernelsProceedings of the Second Workshop on Optimizing Stencil Computations10.1145/2686745.2686748(25-32)Online publication date: 20-Oct-2014
  • (2013)A stencil compiler for short-vector SIMD architecturesProceedings of the 27th international ACM conference on International conference on supercomputing10.1145/2464996.2467268(13-24)Online publication date: 10-Jun-2013
  • (2013)Split tiling for GPUsProceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units10.1145/2458523.2458526(24-31)Online publication date: 16-Mar-2013
  • (2013)PARTANSACM Transactions on Architecture and Code Optimization10.1145/2400682.24007189:4(1-24)Online publication date: 20-Jan-2013
  • (2012)High-performance code generation for stencil computations on GPU architecturesProceedings of the 26th ACM international conference on Supercomputing10.1145/2304576.2304619(311-320)Online publication date: 25-Jun-2012

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