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Multithreaded Value Prediction

Published: 12 February 2005 Publication History

Abstract

This paper introduces a novel technique which leverages value prediction and multithreading on a simultaneous multithreading processor to achieve higher performance in a single threaded application. By allowing the value-speculative execution to proceed in a separate thread, this technique overcomes barriers that make traditional value prediction relatively ineffective for tolerating long latency loads. It shows that this technique can be as much as 2-5 times more effective than traditional value prediction, achieving more than 40% average performance gain on the SPEC benchmarks with realistic hardware parameters. These gains come from two effects: allowing greater separation between the stalled load and the speculative execution, and the ability to speculate on multiple values for a single load.

Cited By

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  • (2018)AVPPACM Transactions on Architecture and Code Optimization10.1145/323956715:4(1-30)Online publication date: 7-Dec-2018
  • (2012)Leveraging Strength-Based Dynamic Information Flow Analysis to Enhance Data Value PredictionACM Transactions on Architecture and Code Optimization10.1145/2133382.21333839:1(1-33)Online publication date: 1-Mar-2012
  • (2010)Energy-performance design space exploration in SMT architectures exploiting selective load value predictionsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1870992(271-274)Online publication date: 8-Mar-2010
  • Show More Cited By

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Published In

cover image Guide Proceedings
HPCA '05: Proceedings of the 11th International Symposium on High-Performance Computer Architecture
February 2005
350 pages
ISBN:0769522750

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IEEE Computer Society

United States

Publication History

Published: 12 February 2005

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Cited By

View all
  • (2018)AVPPACM Transactions on Architecture and Code Optimization10.1145/323956715:4(1-30)Online publication date: 7-Dec-2018
  • (2012)Leveraging Strength-Based Dynamic Information Flow Analysis to Enhance Data Value PredictionACM Transactions on Architecture and Code Optimization10.1145/2133382.21333839:1(1-33)Online publication date: 1-Mar-2012
  • (2010)Energy-performance design space exploration in SMT architectures exploiting selective load value predictionsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1870992(271-274)Online publication date: 8-Mar-2010
  • (2010)The potential of using dynamic information flow analysis in data value predictionProceedings of the 19th international conference on Parallel architectures and compilation techniques10.1145/1854273.1854327(431-442)Online publication date: 11-Sep-2010
  • (2009)Memory-level parallelism aware fetch policies for simultaneous multithreading processorsACM Transactions on Architecture and Code Optimization10.1145/1509864.15098676:1(1-33)Online publication date: 2-Apr-2009
  • (2007)A bypass mechanism to enhance branch predictor for SMT processorsProceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture10.5555/2392163.2392197(364-375)Online publication date: 23-Aug-2007
  • (2006)Enabling real-time physics simulation in future interactive entertainmentProceedings of the 2006 ACM SIGGRAPH symposium on Videogames10.1145/1183316.1183326(71-81)Online publication date: 30-Jul-2006
  • (2006)Tolerating Dependences Between Large Speculative Threads Via Sub-ThreadsACM SIGARCH Computer Architecture News10.1145/1150019.113650434:2(216-226)Online publication date: 1-May-2006
  • (2006)Tolerating Dependences Between Large Speculative Threads Via Sub-ThreadsProceedings of the 33rd annual international symposium on Computer Architecture10.1109/ISCA.2006.43(216-226)Online publication date: 17-Jun-2006

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