research-article

Heterogeneous Chip Multiprocessors

Authors:

Rakesh Kumar,

Dean M. Tullsen,

Norman P. Jouppi,

Parthasarathy RanganathanAuthors Info & Claims

Computer, Volume 38, Issue 11

Pages 32 - 38

https://doi.org/10.1109/MC.2005.379

Published: 01 November 2005 Publication History

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Abstract

Heterogeneous (or asymmetric) chip multiprocessors present unique opportunities for improving system throughput, reducing processor power, and mitigating Amdahl's law. On-chip heterogeneity allows the processor to better match execution resources to each application's needs and to address a wider spectrum of system loads-from low to high thread parallelism-with high efficiency.

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Cited By

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Sen R(2024)Performance or Efficiency? A Tale of Two Cores for DB WorkloadsProceedings of the 20th International Workshop on Data Management on New Hardware10.1145/3662010.3663444(1-5)Online publication date: 10-Jun-2024
https://dl.acm.org/doi/10.1145/3662010.3663444
Mavrogeorgis NVasiladiotis CMu PKhordadi AFranke BBarbalace ARodríguez GSadayappan PSukumaran-Rajam A(2024)UNIFICO: Thread Migration in Heterogeneous-ISA CPUs without State TransformationProceedings of the 33rd ACM SIGPLAN International Conference on Compiler Construction10.1145/3640537.3641565(86-99)Online publication date: 17-Feb-2024
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Naz NZada IMalik ANadeem MAli S(2023)Heterogeneous Hadoop Cluster-Based Image Processing Workload Distribution Framework between CPU and GPUScientific Programming10.1155/2023/12286142023Online publication date: 1-Jan-2023
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Index Terms

Heterogeneous Chip Multiprocessors
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data

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Computer Volume 38, Issue 11

November 2005

94 pages

ISSN:0018-9162

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 November 2005

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Sen R(2024)Performance or Efficiency? A Tale of Two Cores for DB WorkloadsProceedings of the 20th International Workshop on Data Management on New Hardware10.1145/3662010.3663444(1-5)Online publication date: 10-Jun-2024
https://dl.acm.org/doi/10.1145/3662010.3663444
Mavrogeorgis NVasiladiotis CMu PKhordadi AFranke BBarbalace ARodríguez GSadayappan PSukumaran-Rajam A(2024)UNIFICO: Thread Migration in Heterogeneous-ISA CPUs without State TransformationProceedings of the 33rd ACM SIGPLAN International Conference on Compiler Construction10.1145/3640537.3641565(86-99)Online publication date: 17-Feb-2024
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Naz NZada IMalik ANadeem MAli S(2023)Heterogeneous Hadoop Cluster-Based Image Processing Workload Distribution Framework between CPU and GPUScientific Programming10.1155/2023/12286142023Online publication date: 1-Jan-2023
https://dl.acm.org/doi/10.1155/2023/1228614
Reza M(2023)Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core ArchitecturesACM Journal on Emerging Technologies in Computing Systems10.1145/359147019:3(1-26)Online publication date: 30-Jun-2023
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Min DChung YByun IKim JKim JFalsafi BFerdman MLu SWenisch T(2022)CryoWire: wire-driven microarchitecture designs for cryogenic computingProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507749(903-917)Online publication date: 28-Feb-2022
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Cho YPark JNegele FJo CGross TEgger BLee JAgrawal KSpear M(2022)DopiaProceedings of the 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3503221.3508421(32-45)Online publication date: 2-Apr-2022
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Deshwal ABelakaria SBhat GDoppa JPande P(2021)Learning Pareto-Frontier Resource Management Policies for Heterogeneous SoCs: An Information-Theoretic Approach2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586283(607-612)Online publication date: 5-Dec-2021
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Yu TPetoumenos PJanjic VLeather HThomson JMars JTang LXue JWu P(2020)COLAB: a collaborative multi-factor scheduler for asymmetric multicore processorsProceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization10.1145/3368826.3377915(268-279)Online publication date: 22-Feb-2020
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Byun IMin DLee GNa SKim JMartínez JDuato JEeckhout L(2020)CryoCoreProceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture10.1109/ISCA45697.2020.00037(335-348)Online publication date: 30-May-2020
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Abstract

References

Cited By

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Recommendations

Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors

An analysis of on-chip interconnection networks for large-scale chip multiprocessors

A multilayer nanophotonic interconnection network for on-chip many-core communications

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