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Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests

Published: 01 August 1997 Publication History

Abstract

We classify all path-delay faults of a combinational circuit into three categories: {\it singly-testable} (ST), {\it multiply-testable} (MT), and {\it singly-testable\ dependent} (ST-dependent). The classification uses any unaltered single stuck-at fault test generation tool. Only two runs of this tool on a model network derived from the original network are performed. As a by-product of this process, we generate single and multiple input change delay tests for all testable faults. With these tests, we expect that most defective circuits are identified. All ST faults are guaranteed detection in the case of a single fault, and some may be guaranteed detection through robust and validatable non-robust tests even in the case of multiple faults. An ST-dependent fault can affect the circuit speed only if certain ST faults are present. Thus, if all ST faults are tested, the ST-dependent faults need not be tested. MT faults cannot be guaranteed detection, but affect the speed only if delay faults simultaneously exist on a set of paths, none of which is ST. Examples and results on several ISCAS ‘89 benchmarks are presented. The method of classification through test generation using a model network is complex and can be applied to circuits of moderate size. For larger circuits, alternative methods will have to be explored in the future.

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Cited By

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  • (2012)Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay FaultsACM Transactions on Design Automation of Electronic Systems10.1145/2348839.234885117:4(1-20)Online publication date: 1-Oct-2012
  • (2007)Efficient path delay test generation based on stuck-at test generation using checker circuitryProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326160(418-423)Online publication date: 5-Nov-2007
  • (2007)Hardware-accelerated path-delay fault grading of functional test programs for processor-based systemsProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228881(411-416)Online publication date: 11-Mar-2007
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        Published In

        cover image Journal of Electronic Testing: Theory and Applications
        Journal of Electronic Testing: Theory and Applications  Volume 11, Issue 1
        Special issue on test synthesis
        Aug. 1997
        94 pages
        ISSN:0923-8174
        Issue’s Table of Contents

        Publisher

        Kluwer Academic Publishers

        United States

        Publication History

        Published: 01 August 1997

        Author Tags

        1. delay test
        2. digital circuit testing
        3. fault models
        4. path delay faults
        5. test generation

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        View all
        • (2012)Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay FaultsACM Transactions on Design Automation of Electronic Systems10.1145/2348839.234885117:4(1-20)Online publication date: 1-Oct-2012
        • (2007)Efficient path delay test generation based on stuck-at test generation using checker circuitryProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326160(418-423)Online publication date: 5-Nov-2007
        • (2007)Hardware-accelerated path-delay fault grading of functional test programs for processor-based systemsProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228881(411-416)Online publication date: 11-Mar-2007
        • (2007)Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τk-NotationIEICE - Transactions on Information and Systems10.1093/ietisy/e90-d.8.1202E90-D:8(1202-1212)Online publication date: 1-Aug-2007
        • (2007)System-on-Chip Test ArchitecturesundefinedOnline publication date: 20-Nov-2007
        • (2005)Propagation delay faultProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120799(178-183)Online publication date: 18-Jan-2005
        • (2005)The coupling model for function and delay faultsJournal of Electronic Testing: Theory and Applications10.1007/s10836-005-3476-y21:6(631-649)Online publication date: 1-Dec-2005
        • (2004)A new classification of path-delay fault testability in terms of stuck-at faultsJournal of Computer Science and Technology10.1007/BF0297346019:6(955-964)Online publication date: 1-Nov-2004
        • (2003)A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation AlgorithmsProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022743Online publication date: 3-Mar-2003
        • (2000)Universal Test Generation Using Fault TuplesProceedings of the 2000 IEEE International Test Conference10.5555/839295.843543Online publication date: 3-Oct-2000
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