A PUS based nets weighting mechanism for power, hold, and setup timing optimization

Power consumption has become a major constraint in VLSI design. A considerable power increase is usually seen during the hold closure step of the physical design done in post-CTS and post-route stages. Hold optimization is performed by applying some circuit-level changes such as buffer insertion, cell sizing, useful-skew or cell movement. Moving the hold fixing problem to the pre-CTS stage represents a big opportunity for power saving and design closure improvement. In this paper, we present a novel power, hold, and setup driven placement algorithm. The objective is to reduce not only the setup, but also the hold violations while keeping the power consumption under control. This objective is achieved by changing the weighting mechanism of a commercial Power and Timing Driven Placement (PTDP) engine to include power, hold and electrical Design Rule Constraints (eDRC) in the weighting equation which will drive the placer to place the cells that are in the setup critical paths or connected with high power nets close to each other and relax the weight of the cells that are on hold critical paths, so the placer may place them far from each other. As a consequence, critical setup, power or eDRC nets will be shortened to reduce the delay, and critical hold nets will be elongated to add delay and hence improve the placement overall Quality of Results (QoR). This approach was deployed on 40 industrial designs of different customers, sizes, technologies, and complexities and showed very good improvement, not only in timing (setup and hold) and power consumption but also in total area and design routability. The timing gain is about 15% and 13% in TNS and THS respectively. The total power gain is about 9%, distributed as 7% in leakage power and 9% in dynamic power.