Article

A high-performance implementation of differential power analysis on graphics cards

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CARDIS'11: Proceedings of the 10th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications

Pages 252 - 265

https://doi.org/10.1007/978-3-642-27257-8_16

Published: 14 September 2011 Publication History

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Abstract

We present an implementation for Differential Power Analysis (DPA) that is entirely based on Graphics Processing Units (GPUs). In this paper we make use of advanced techniques offered by the CUDA Framework in order to minimize the runtime. In security testing DPA still plays a major role for the smart card industry and these evaluations require, apart from educationally prepared measurement setups, the analysis of measurements with large amounts of traces and samples, and here time does matter. Most often DPA implementations are tailor-made and adapted to fit certain platforms and hence efficient reference implementations are sparsely seeded. In this work we show that the powerful architecture of graphics cards is well suited to facilitate a DPA implementation, based on the Pearson correlation coefficient, that could serve as a high performant reference, e.g., by analyzing one million traces of 20<em>k</em> samples in less than two minutes.

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Cited By

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Liu BQiu WJiang LGong Z(2016)Software pipelining for graphic processing unit accelerationInternational Journal of High Performance Computing Applications10.1177/109434201558584530:2(169-185)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1177/1094342015585845
Swamy TShah NLuo PFei YKaeli DLee RShi W(2014)Scalable and efficient implementation of correlation power analysis using graphics processing units (GPUs)Proceedings of the Third Workshop on Hardware and Architectural Support for Security and Privacy10.1145/2611765.2611775(1-8)Online publication date: 15-Jun-2014
https://dl.acm.org/doi/10.1145/2611765.2611775
Lomné VProuff ERoche T(2013)Behind the Scene of Side Channel AttacksPart I of the Proceedings of the 19th International Conference on Advances in Cryptology - ASIACRYPT 2013 - Volume 826910.1007/978-3-642-42033-7_26(506-525)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1007/978-3-642-42033-7_26

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CARDIS'11: Proceedings of the 10th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications

September 2011

336 pages

ISBN:9783642272561

Editor:
Emmanuel Prouff
Oberthur Technologies, 71-73 rue des Hautes Pâtures, Nanterre Cedex, France

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 14 September 2011

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Liu BQiu WJiang LGong Z(2016)Software pipelining for graphic processing unit accelerationInternational Journal of High Performance Computing Applications10.1177/109434201558584530:2(169-185)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1177/1094342015585845
Swamy TShah NLuo PFei YKaeli DLee RShi W(2014)Scalable and efficient implementation of correlation power analysis using graphics processing units (GPUs)Proceedings of the Third Workshop on Hardware and Architectural Support for Security and Privacy10.1145/2611765.2611775(1-8)Online publication date: 15-Jun-2014
https://dl.acm.org/doi/10.1145/2611765.2611775
Lomné VProuff ERoche T(2013)Behind the Scene of Side Channel AttacksPart I of the Proceedings of the 19th International Conference on Advances in Cryptology - ASIACRYPT 2013 - Volume 826910.1007/978-3-642-42033-7_26(506-525)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1007/978-3-642-42033-7_26

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Full lattice basis reduction on graphics cards

A performance study of general-purpose applications on graphics processors using CUDA

Massively parallel differential evolution--pattern search optimization with graphics hardware acceleration: an investigation on bound constrained optimization problems

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