article

Simulation-based performance analysis of an ultra-low specific on-resistance trench SOI LDMOS with a floating vertical field plate

Authors:

Fang TangAuthors Info & Claims

Journal of Computational Electronics, Volume 16, Issue 1

Pages 83 - 89

https://doi.org/10.1007/s10825-017-0955-1

Published: 01 March 2017 Publication History

Abstract

An ultra-low specific on-resistance $$(R_\mathrm{{on,sp}})$$(Ron,sp) trench SOI LDMOS with a floating vertical field plate structure (FVFPT SOI) is proposed in this paper. A floating vertical plate (FVFP) is introduced into the filled oxide trench of a conventional trench SOI LDMOS (CT SOI) to improve its electrical performance. We conduct related performance analysis to this device by simulation and investigate the effects of different parameters on its performance. The FVFP causes an assisted depletion effect especially for the trench surface regions. An ultra-low $$R_\mathrm{{on,sp}}$$Ron,sp is therefore obtained in the FVFP device due to higher drift region doping concentration $$(N_\mathrm{{d}})$$(Nd). A breakdown voltage (BV) of 188V and a $$R_\mathrm{{on,sp}}$$Ron,sp of $$0.9 \hbox { m}\Omega \, \hbox { cm}^{2}$$0.9mΩcm2 are realized on a 4.8-$${\upmu }\hbox {m}$$μm-long drift region, a 7.5-$${\upmu }\hbox {m}$$μm-thick top-silicon layer and a 0.5-$${\upmu }\hbox {m}$$μm-thick buried oxide (BOX) layer by our simulation. Eventually, the $$R_\mathrm{{on,sp}}$$Ron,sp for the FVFPT SOI can be reduced by more than 60%, while its BV is maintained the same class as the CT SOI, and the figure of merit (FOM) is enhanced by 155%. And a set of optimal parameters, including the structure parameters of plate and the property parameters of device, are obtained.

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Cited By

Lei JHu SYang DHuang YYuan QGuo JZeng LWang SYang X(2018)Investigation of a novel SOI LDMOS using p+ buried islands in the drift region by numerical simulationsJournal of Computational Electronics10.1007/s10825-018-1168-y17:2(646-652)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.1007/s10825-018-1168-y

Simulation-based performance analysis of an ultra-low specific on-resistance trench SOI LDMOS with a floating vertical field plate
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cover image Journal of Computational Electronics

Journal of Computational Electronics Volume 16, Issue 1

March 2017

219 pages

ISSN:1569-8025

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Copyright © Copyright © 2017 Springer Science+Business Media New York.

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 01 March 2017

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Cited By

Lei JHu SYang DHuang YYuan QGuo JZeng LWang SYang X(2018)Investigation of a novel SOI LDMOS using p+ buried islands in the drift region by numerical simulationsJournal of Computational Electronics10.1007/s10825-018-1168-y17:2(646-652)Online publication date: 21-Dec-2018
https://dl.acm.org/doi/10.1007/s10825-018-1168-y

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