Cited By
View all- Punetha MSingh Y(2018)Dual-channel trench LDMOS on SOI for RF power amplifier applicationsJournal of Computational Electronics10.1007/s10825-015-0776-z15:2(639-645)Online publication date: 21-Dec-2018
Controlling the ON-resistance in SOI LDMOS using parasitic bipolar junction transistor
Pages 857 - 861
Abstract
We present a new parasitic bipolar junction transistor (BJT) enhanced silicon on insulator (SOI) laterally double diffused metal oxide semiconductor (LDMOS), called BJT enhanced LDMOS (BE-LDMOS). The proposed device utilizes the parasitic BJT present in an LDMOS to increase the drain current for a given gate voltage, resulting in a reduction in the ON-resistance by 26.2 % and improving the switching speed by 7.8 % for BE-LDMOS as compared to the comparable LDMOS. These improvements are without degradation in other performance parameters such as off state breakdown voltage and transconductance. The process steps for fabricating BE-LDMOS are same as that for LDMOS except for an additional metal contact.
References
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Sithanandam, R., Kumar, M.J.: Linearity and speed optimization in SOI LDMOS using gate engineering. Semicond. Sci. Technol. 25(1), 015006 (Jan. 2010)
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- Controlling the ON-resistance in SOI LDMOS using parasitic bipolar junction transistor
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Copyright © Copyright © 2014 Springer Science+Business Media New York.
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Berlin, Heidelberg
Publication History
Published: 01 December 2014
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View all- Punetha MSingh Y(2018)Dual-channel trench LDMOS on SOI for RF power amplifier applicationsJournal of Computational Electronics10.1007/s10825-015-0776-z15:2(639-645)Online publication date: 21-Dec-2018
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