This dissertation introduces software thread integration (STI) and its use for migrating functions from hardware to software (HSM). STI interleaves multiple software threads at the assembly language level, offering efficient concurrency for general-purpose processors. This concurrency is invaluable for HSM, which requires concurrent execution of multiple real-time software threads. STI provides a set of compiler-implemented code transformations which produce efficient code. Putting the transformations into a compiler lets the system developer work at a higher level and therefore with more efficiency.
Existing methods of HSM suffer from a complicated manual process and inefficient output code. Despite these limits, embedded system designers frequently perform HSM to meet design goals. STI provides a mechanism for efficiently sharing the CPU by interleaving multiple real-time software threads into an integrated thread, replacing context switching and busy waiting with useful instructions to raise efficiency. It uses code transformations which can be automated and implemented in a post-pass compiler. This automation lets system developers perform HSM much more efficiently, reducing development time and effort. Timing accuracy, run-time overhead and code size can be traded off to meet a specific embedded system's goals.
This dissertation contributes automatic methods for guiding, performing, and evaluating STI and HSM. It begins by presenting the code transformations needed to integrate real-time threads. These transformations are implemented in a compiler to automate integration and speed migration. The code produced is more efficient than that of other methods and can be optimized for program size or speed. It shows how to measure thread suitability for integration based upon idle time distribution and segment timing determinacy. It then presents a method to select threads for integration based upon these metrics and profiling information, and then predict the resulting system performance and memory cost. It introduces methods for linking a trigger event with the execution of service thread. These methods allow a system designer to trade off efficiency for response latency. Finally, this dissertation also presents other benefits of STI such as concurrent error detection and performance enhancement.
Cited By
- So W and Dean A (2013). Software thread integration for instruction-level parallelism, ACM Transactions on Embedded Computing Systems (TECS), 13:1, (1-23), Online publication date: 1-Aug-2013.
- Zhou X and Petrov P (2009). Cross-layer customization for rapid and low-cost task preemption in multitasked embedded systems, ACM Transactions on Embedded Computing Systems (TECS), 8:2, (1-28), Online publication date: 1-Jan-2009.
- Shivshankar S, Vangara S and Dean A Balancing register pressure and context-switching delays in ASTI systems Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, (286-294)
- Asokan V and Dean A Providing time- and space- efficient procedure calls for asynchronous software thread integration Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, (167-178)
- Kumar N, Shivshankar S and Dean A Asynchronous software thread integration for efficient software Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, (37-46)
- Kumar N, Shivshankar S and Dean A (2019). Asynchronous software thread integration for efficient software, ACM SIGPLAN Notices, 39:7, (37-46), Online publication date: 11-Jul-2004.
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