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Compile-time memory disambiguation for c programs
Publisher:
  • University of Illinois at Urbana-Champaign
  • Champaign, IL
  • United States
ISBN:978-0-599-76189-6
Order Number:AAI9971049
Pages:
148
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Abstract

Static memory disambiguation is a compile-time technique which determines whether or not two memory instructions access the same memory location at run-time. With fully disambiguated memory accesses, instruction scheduling and code optimization can be conducted in a much more aggressive manner. As the speed gap between the processor and memory widens, the value of optimized memory accesses will scale accordingly. To disambiguate memory accesses beyond scalar local variables, a critical task in an optimizing compiler is to perform interprocedural pointer analysis in order to handle indirect memory accesses through pointers in the presence of function calls with side-effects. Interprocedural pointer analysis has long been considered as too expensive to afford. Therefore unlike function inlining, register allocation, and SSA analysis, interprocedural pointer analysis has not been integrated into commercial compilers. The core of this dissertation is a new modular interprocedural pointer analysis algorithm which significantly improves the feasibility of static memory disambiguation. The proposed algorithm can handle much larger C programs with realistic language features. Due to its modular feature, the amounts of time and memory requirements are greatly reduced. The dissertation also evaluates the effectiveness of the proposed algorithm on the complete SPECcint92 and SPECcint95 benchmark suites. Significant performance improvements are observed from these pointer-intensive programs.

Cited By

  1. Gibert E, Sanchez J and Gonzalez A (2005). Distributed Data Cache Designs for Clustered VLIW Processors, IEEE Transactions on Computers, 54:10, (1227-1241), Online publication date: 1-Oct-2005.
  2. Gibert E, Sánchez J and González A Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
  3. Gibert E, Sánchez J and González A Local scheduling techniques for memory coherence in a clustered VLIW processor with a distributed data cache Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, (193-203)
  4. Gibert E, Sánchez J and González A Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, (123-133)
  5. Chen T, Lin J, Hsu W and Yew P An empirical study on the granularity of pointer analysis in c programs Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing, (157-171)
  6. ACM
    Gibert E, Sánchez J and González A An interleaved cache clustered VLIW processor Proceedings of the 16th international conference on Supercomputing, (210-219)
  7. ACM
    Cheng B and Hwu W Modular interprocedural pointer analysis using access paths Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation, (57-69)
  8. ACM
    Cheng B and Hwu W (2019). Modular interprocedural pointer analysis using access paths, ACM SIGPLAN Notices, 35:5, (57-69), Online publication date: 1-May-2000.
Contributors
  • University of Illinois Urbana-Champaign
  • Transmeta Corporation
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