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Fast Secure Processor for Inhibiting Software Piracy and Tampering

Published: 03 December 2003 Publication History

Abstract

Due to the widespread software piracy and virus attacks,significant efforts have been made to improve security forcomputer systems. For stand-alone computers, a key observationis that other than the processor, any component isvulnerable to security attacks. Recently, an execution onlymemory (XOM) architecture has been proposed to supportcopy and tamper resistant software [18, 17, 13]. In this design,the program and data are stored in encrypted formatoutside the CPU boundary. The decryption is carried afterthey are fetched from memory, and before they are used bythe CPU. As a result, the lengthened critical path causes aserious performance degradation.In this paper, we present an innovative technique inwhich the cryptography computation is shifted off from thememory access critical path. We propose to use a differentencryption scheme, namely "one-time pad" encryption, toproduce the instructions and data ciphertext. With someadditional on-chip storage, cryptography computations arecarried in parallel with memory accesses, minimizing performancepenalty. We performed experiments to study thetrade-off between storage size and performance penalty.Our technique improves the execution speed of the XOMarchitecture by 34.7% at maximum.

References

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  • (2022)MGXProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527418(726-741)Online publication date: 18-Jun-2022
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  • (2021)Bonsai Merkle Forests: Efficiently Achieving Crash Consistency in Secure Persistent MemoryMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480067(1227-1240)Online publication date: 18-Oct-2021
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Information

Published In

cover image ACM Conferences
MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
December 2003
412 pages
ISBN:076952043X

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IEEE Computer Society

United States

Publication History

Published: 03 December 2003

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MICRO 36 Paper Acceptance Rate 35 of 134 submissions, 26%;
Overall Acceptance Rate 484 of 2,242 submissions, 22%

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Cited By

View all
  • (2022)MGXProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527418(726-741)Online publication date: 18-Jun-2022
  • (2022)SoftVNProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527378(160-172)Online publication date: 18-Jun-2022
  • (2021)Bonsai Merkle Forests: Efficiently Achieving Crash Consistency in Secure Persistent MemoryMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480067(1227-1240)Online publication date: 18-Oct-2021
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  • (2017)InvisiMemACM SIGARCH Computer Architecture News10.1145/3140659.308023245:2(94-106)Online publication date: 24-Jun-2017
  • (2017)PagevaultProceedings of the International Symposium on Memory Systems10.1145/3132402.3132439(293-304)Online publication date: 2-Oct-2017
  • (2017)InvisiMemProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080232(94-106)Online publication date: 24-Jun-2017
  • (2016)PoisonivyThe 49th Annual IEEE/ACM International Symposium on Microarchitecture10.5555/3195638.3195684(1-13)Online publication date: 15-Oct-2016
  • (2016)Reducing the Memory Bandwidth Overheads of Hardware Security Support for Multi-Core ProcessorsIEEE Transactions on Computers10.1109/TC.2016.253821865:11(3384-3397)Online publication date: 1-Nov-2016
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