Article

Reconfigurable Instruction Set Processors: A Survey

Authors:

Francisco Barat,

Rudy LauwereinsAuthors Info & Claims

RSP '00: Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)

Page 168

Published: 21 June 2000 Publication History

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Abstract

Reconfigurable instruction set processors have the capability to adapt their instruction sets to the application being executed through a reconfiguration in their hardware. Through this adaptation, they are expected to achieve a great improvement in performance compared to fixed instruction set processors. In this paper, we discuss the different hardware aspects that have to be considered during the design of such a reconfigurable processor. The topics discussed include the coupling of the processor and the reconfigurable logic, configuration, instruction coding and scheduling, granularity, hardware cache and reconfigurability. A classification of current reconfigurable processors is done according to the discussed topics.

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Hoffmann JGüttler FEl-Laithy KBogdan M(2012)Cyfield-RISPProceedings of the 22nd international conference on Artificial Neural Networks and Machine Learning - Volume Part I10.1007/978-3-642-33269-2_22(169-176)Online publication date: 11-Sep-2012
https://dl.acm.org/doi/10.1007/978-3-642-33269-2_22
Galuzzi CBertels K(2011)The Instruction-Set Extension ProblemACM Transactions on Reconfigurable Technology and Systems10.1145/1968502.19685094:2(1-28)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1968502.1968509
Kim YMahapatra RChoi K(2010)Design space exploration for efficient resource utilization in coarse-grained reconfigurable architectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202528018:10(1471-1482)Online publication date: 1-Oct-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2025280
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Published In

RSP '00: Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)

June 2000

ISBN:0769506682

Publisher

IEEE Computer Society

United States

Publication History

Published: 21 June 2000

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Hoffmann JGüttler FEl-Laithy KBogdan M(2012)Cyfield-RISPProceedings of the 22nd international conference on Artificial Neural Networks and Machine Learning - Volume Part I10.1007/978-3-642-33269-2_22(169-176)Online publication date: 11-Sep-2012
https://dl.acm.org/doi/10.1007/978-3-642-33269-2_22
Galuzzi CBertels K(2011)The Instruction-Set Extension ProblemACM Transactions on Reconfigurable Technology and Systems10.1145/1968502.19685094:2(1-28)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1968502.1968509
Kim YMahapatra RChoi K(2010)Design space exploration for efficient resource utilization in coarse-grained reconfigurable architectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202528018:10(1471-1482)Online publication date: 1-Oct-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2025280
Kim YMahapatra R(2010)Dynamic context compression for low-power coarse-grained reconfigurable architectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200684618:1(15-28)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2006846
Guha RBagherzadeh NChou P(2009)Resource management and task partitioning and scheduling on a run-time reconfigurable embedded systemComputers and Electrical Engineering10.1016/j.compeleceng.2008.06.00835:2(258-285)Online publication date: 1-Mar-2009
https://dl.acm.org/doi/10.1016/j.compeleceng.2008.06.008
Bauer LShafique MKreutz SHenkel JSciuto D(2008)Run-time system for an extensible embedded processor with dynamic instruction setProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403558(752-757)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403558
Bauer LShafique MHenkel JFix L(2008)Run-time instruction set selection in a transmutable embedded processorProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391486(56-61)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391486
Bauer LShafique MKramer SHenkel JLevitan S(2007)RISPPProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278678(791-796)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278678
Kim YPark IChoi KPaek YNebel WStan MRaghunathan AHenkel JMarculescu D(2006)Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architectureProceedings of the 2006 international symposium on Low power electronics and design10.1145/1165573.1165646(310-315)Online publication date: 4-Oct-2006
https://dl.acm.org/doi/10.1145/1165573.1165646
Veale BAntonio JTull M(2005)Configuration Steering for a Reconfigurable Superscalar ProcessorProceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 0410.1109/IPDPS.2005.148Online publication date: 4-Apr-2005
https://dl.acm.org/doi/10.1109/IPDPS.2005.148
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Improving performance and energy efficiency of embedded processors via post-fabrication instruction set customization

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Reconfigurable Instruction Set Processors from a Hardware/Software Perspective

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