S-1 architecture manualJanuary 1979
- Authors:
- Brent T. Hailpern,
- Bruce L. Hitson
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Abstract
This manual provides a complete description of the instruction-set architecture of the S-1 Uniprocessor (Mark IIA), exclusive of vector operations. It is assumed that the reader has a general knowledge of computer architecture. The manual was designed to be both a detailed introduction to the S-1 and an architecture reference manual. Also included are user manuals for the FASM Assembler and the S-1 Formal Description Syntax.
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- Steele G and Gabriel R The evolution of Lisp History of programming languages---II, (233-330)
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- Thakkar S and Hostmann W (2019). An instruction fetch unit for a graph reduction machine, ACM SIGARCH Computer Architecture News, 14:2, (82-91), Online publication date: 1-May-1986.
- Thakkar S and Hostmann W An instruction fetch unit for a graph reduction machine Proceedings of the 13th annual international symposium on Computer architecture, (82-91)
- Hill M and Smith A (2019). Experimental evaluation of on-chip microprocessor cache memories, ACM SIGARCH Computer Architecture News, 12:3, (158-166), Online publication date: 1-Jun-1984.
- Hill M and Smith A Experimental evaluation of on-chip microprocessor cache memories Proceedings of the 11th annual international symposium on Computer architecture, (158-166)
- Steele G An overview of COMMON LISP Proceedings of the 1982 ACM symposium on LISP and functional programming, (98-107)
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