Article

Free access

Automatic test vector generation for mixed-signal circuits

Authors:

B. Ayari,

N. Ben Hamida,

B. KaminskaAuthors Info & Claims

EDTC '95: Proceedings of the 1995 European conference on Design and Test

Page 458

Published: 06 March 1995 Publication History

PDF eReader

Abstract

Mixed circuit testing is known to be a very difficult task. This is due to the difficulty of: testing the analog part of the circuit, controlling the digital signal from the analog outputs, observing the analog outputs in the digital circuit, controlling the analog circuit from the digital outputs and observing the digital signals in the analog circuit. As a solution to these problems, we propose an automatic test vector generation for mixed circuits to perform functional testing. In this paper, a case of an analog block followed by a digital block is considered. The experimental results (simulation and discrete realization) show the efficiency of the automatic test generation technique.

References

[1]

{1} D. K. Shirachi "Codec Testing Using Synchronized Analog and Digital Signnal", ITC, 1984, pp. 447-454.

Google Scholar

[2]

{2} R. Kramer "Testing Mixed-Signal Devices" IEEE Design and Test, Apr. 1987. pp. 12-20.

Digital Library

Google Scholar

[3]

{3} S. Max, "Fast, Accurate, And Complete ADC Testing" Int'l Test Conf., 1989.

Google Scholar

[4]

{4} K. D. Wagner and T. W. Williams "Design For Testability of Mixed-Signal Integrated Circuits" Int'l Test Conf., 1988, pp. 823-828.

Google Scholar

[5]

{5} P. Fassang, D. Mullins and T. Wang "Design For Testability For Mixed-Signal ASICs". IEEE Custom Integrated Circuits Conf., 1988, pp. 16.5.1-4.

Google Scholar

[6]

{6} "P1149.4 Mixed-Signal Test Bus Framework Proposal" Panel session, IEEE International Test Conf., 1992, pp. 554-556.

Digital Library

Google Scholar

[7]

{7} A. F. Alani, G. Musgrave and A. P. Ambler "A Stady-State Response Test Generation For Mixed-Signal Integrated Circuits" IEEE International Test Conference, 1992. pp. 415-421.

Digital Library

Google Scholar

[8]

{8} Naim BenHamida and Bozena Kaminska, "Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling", IEEE International Test Conference, Oct. 1993.

Digital Library

Google Scholar

[9]

{9} L. Milor and V. Visavanathan. "Detection of Catastrophic Faults in Analog Circuits." IEEE Trans. Computer Aided Design, Vol. CAD-8 No. 2 Feb. 1989, pp. 114-130.

Digital Library

Google Scholar

[10]

{10} Bechir Ayari and Bozena Kaminska "BDD_FTEST: Fast. Backtrack-Free Test Generator Based on Binary Decision Diagram Representation" submitted to Transaction on CAD.

Google Scholar

[11]

{11} F. Berglez and H. Fujiwara, "A Neural Netlist of 10 Combinational Benchmark Designs and a special Translator in Fortran" Int'l Symposium on Circuits and Systems, june 1985.

Google Scholar

[12]

{12} N. Nagi and J. A. Abraham, "Hierarchical fault modeling for analog and mixed-signal circuits", IEEE VLSI Test Symposium 1992. pp. 96-101.

Crossref

Google Scholar

[13]

{13} A. Meixner and W. Maly, "Fault modeling for the testing of mixed integrated circuits" International Test Conference 1991. pp. 564-572.

Digital Library

Google Scholar

Cited By

View all

Khouas ADerieux A(2019)Fault Simulation for Analog Circuits Under Parameter VariationsJournal of Electronic Testing: Theory and Applications10.1023/A:100835160102416:3(269-278)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1023/A%3A1008351601024
Khouas ADerieux A(1999)Speed-up of High Accurate Analog Test Stimulus OptimizationProceedings of the 1999 IEEE International Test Conference10.5555/518925.939367Online publication date: 28-Sep-1999
https://dl.acm.org/doi/10.5555/518925.939367
Carro LNegreiros MChawla BBryant RRabaey J(1998)Efficient analog test methodology based on adaptive algorithmsProceedings of the 35th annual Design Automation Conference10.1145/277044.277051(32-37)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1145/277044.277051
Show More Cited By

Automatic test vector generation for mixed-signal circuits
1. Hardware

Recommendations

Test generation for mixed-signal devices using signal flow graphs
VLSID '96: Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

We describe a new reverse simulation approach to analog and mixed-circuit test generation that parallels the digital test generation process. We invert the signal flow graph of the analog circuit, reverse simulate it with good and bad machine outputs, ...
Defect-oriented test methodology for complex mixed-signal circuits
EDTC '95: Proceedings of the 1995 European conference on Design and Test

Testing of analog blocks in digital circuits is emerging as a critical factor in the success of mixed-signal ICs. The present specification-oriented testing of these blocks results in high test costs and doesn't ensure detection of all defects, causing ...
Test generation for cyclic combinational circuits
VLSID '95: Proceedings of the 8th International Conference on VLSI Design

Circuits that have an underlying acyclic topology are guaranteed to be combinational since feedback is necessary for sequential behavior. However, the reverse is not true, i.e., feedback is not a sufficient condition since there do exist combinational ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

EDTC '95: Proceedings of the 1995 European conference on Design and Test

March 1995

556 pages

ISBN:0818670398

Publisher

IEEE Computer Society

United States

Publication History

Published: 06 March 1995

Check for updates

Author Tags

Qualifiers

Article

Conference

EDTC95

Sponsor:

SIGDA

EDTC95: European Design and Test Conference

March 6 - 9, 1995

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
155
Total Downloads

Downloads (Last 12 months)18
Downloads (Last 6 weeks)10

Reflects downloads up to 24 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Khouas ADerieux A(2019)Fault Simulation for Analog Circuits Under Parameter VariationsJournal of Electronic Testing: Theory and Applications10.1023/A:100835160102416:3(269-278)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1023/A%3A1008351601024
Khouas ADerieux A(1999)Speed-up of High Accurate Analog Test Stimulus OptimizationProceedings of the 1999 IEEE International Test Conference10.5555/518925.939367Online publication date: 28-Sep-1999
https://dl.acm.org/doi/10.5555/518925.939367
Carro LNegreiros MChawla BBryant RRabaey J(1998)Efficient analog test methodology based on adaptive algorithmsProceedings of the 35th annual Design Automation Conference10.1145/277044.277051(32-37)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1145/277044.277051
Jaworski ZNiewczas MKuzmicz W(1997)Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test GenerationProceedings of the 15th IEEE VLSI Test Symposium10.5555/832297.836370Online publication date: 27-Apr-1997
https://dl.acm.org/doi/10.5555/832297.836370

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Recommendations

Test generation for mixed-signal devices using signal flow graphs

Defect-oriented test methodology for complex mixed-signal circuits

Test generation for cyclic combinational circuits