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Computer Logic, Testing and VerificationApril 1980
- Author:
- J. Paul Roth
Abstract
No abstract available.
Cited By
- Xu J, Ye S, Zhang W, Wei J and Huang T VM image update notification mechanism based on pub/sub paradigm in cloud Proceedings of the 5th Asia-Pacific Symposium on Internetware, (1-4)
- Hiller M, Jhumka A and Suri N (2004). EPIC, IEEE Transactions on Computers, 53:5, (512-530), Online publication date: 1-May-2004.
- Fallah F Binary time-frame expansion Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, (458-464)
- Hiller M, Jhumka A and Suri N An Approach for Analysing the Propagation of Data Errors in Software Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS), (161-172)
- Wang Y and McCrosky C (1996). Negation Trees, IEEE Transactions on Computers, 45:5, (626-630), Online publication date: 1-May-1996.
- Struss P Testing physical systems Proceedings of the Twelfth AAAI National Conference on Artificial Intelligence, (251-256)
- Bryant R Symbolic simulation—techniques and applications Proceedings of the 27th ACM/IEEE Design Automation Conference, (517-521)
- Fleisher H, Giraldi J, Phoenix R and Tavel M (2019). Minimizability of Random Boolean Functions, IEEE Transactions on Computers, 38:4, (593-595), Online publication date: 1-Apr-1989.
- Coppola A New methods in the analysis of logic minimization data and algorithms Proceedings of the 26th ACM/IEEE Design Automation Conference, (226-231)
- Cho K and Bryant R Test pattern generation for sequential MOS circuits by symbolic fault simulation Proceedings of the 26th ACM/IEEE Design Automation Conference, (418-423)
- Savir J Why partial design verification works better than it should Proceedings of the 25th ACM/IEEE Design Automation Conference, (704-707)
- Helliwell M and Perkowski M A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms Proceedings of the 25th ACM/IEEE Design Automation Conference, (427-432)
- Devadas S, Ma H and Newton A On the verification of sequential machines at differing levels of abstraction Proceedings of the 24th ACM/IEEE Design Automation Conference, (271-276)
- Ma H, Devadas S, Sangiovanni-Vincentelli A and Wei R Logic verification algorithms and their parallel implementation Proceedings of the 24th ACM/IEEE Design Automation Conference, (283-290)
- Fleisher H, Tavel M and Yeager J (1987). A Computer Algorithm for Minimizing Reed-Muller Canonical Forms, IEEE Transactions on Computers, 36:2, (247-250), Online publication date: 1-Feb-1987.
- Daehn W A unified treatment of PLA faults by Boolean differences Proceedings of the 23rd ACM/IEEE Design Automation Conference, (334-338)
- Roth J (1986). Minimization by the D Algorithm, IEEE Transactions on Computers, 35:5, (476-478), Online publication date: 1-May-1986.
- Bryant R (1986). Graph-Based Algorithms for Boolean Function Manipulation, IEEE Transactions on Computers, 35:8, (677-691), Online publication date: 1-Aug-1986.
- Wei R and Sangiovanni-Vincentelli A PLATYPUS Proceedings of the 22nd ACM/IEEE Design Automation Conference, (197-203)
- Bryant R Symbolic manipulation of Boolean functions using a graphical representation Proceedings of the 22nd ACM/IEEE Design Automation Conference, (688-694)
- Sasao T (1984). Input Variable Assignment and Output Phase Optimization of PLA's, IEEE Transactions on Computers, 33:10, (879-894), Online publication date: 1-Oct-1984.
- Pfister G Parallel processing, special-purpose hardware, and DA applications Proceedings of the 1983 computer science conference, (21-24)
- Somenzi F, Gai S, Mezzalama M and Prinetto P A new integrated system for PLA testing and verification Proceedings of the 20th Design Automation Conference, (57-63)
- Brand D (1983). Redundancy and Don't Cares in Logic Synthesis, IEEE Transactions on Computers, 32:10, (947-952), Online publication date: 1-Oct-1983.
- Hachtel G, Newton A and Sangiovanni-Vincentelli A Techniques for programmable logic array folding Proceedings of the 19th Design Automation Conference, (147-155)
- Lightner M and Hachtel G Implication algorithms for MOS switch level functional macromodeling implication and testing Proceedings of the 19th Design Automation Conference, (691-698)
- Leinwand S Logical correctness by construction Proceedings of the 19th Design Automation Conference, (825-831)
- Levendel Y and Menon P (1982). Test Generation Algorithms for Computer Hardware Description Languages, IEEE Transactions on Computers, 31:7, (577-588), Online publication date: 1-Jul-1982.
- Berman L On logic comparison Proceedings of the 18th Design Automation Conference, (854-861)
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