Browse Books

Reviewer: Sajjan G. Shiva

This tutorial on the Verilog hardware description language consists of ten chapters and seven appendices, the last of which provides the formal syntax of the language. Chapter 1 is a tutorial introduction to the major features of Verilog. It covers the behavior modeling of combinational and sequential circuits, hierarchical modeling concepts, finite state machines and data paths, and cycle-accurate descriptions. The chapter is well written and includes example descriptions. It forms a good tutorial not only on Verilog, but also on logic design using hardware description languages. Chapter 2 provides the details of behavioral modeling. It introduces the process model and corresponding Verilog constructs (if-then-else, case, loop, multiway branch, functions and tasks, and scope rules). Chapter 3 extends the concepts presented in chapter 2 to the modeling of concurrent processes. It covers event modeling, wait statements, intra-assignment control and timing events, procedural continuous assignment, and sequential and parallel blocks. The example of a simple pipelined processor reinforces these concepts. Chapter 4 is an introduction to modeling at the logic level. It covers the modeling of logic gates and nets, instance arrays, parameterized definitions, delay modeling, and intermodule delay concepts. A mixed behavioral/structural modeling example ties the concepts together. Chapter 5 deals with advanced timing concepts. It provides the basic model of a simulator, followed by a good description of the nondeterministic behavior of simulation algorithms and the concept of nonblocking procedural assignments. Chapter 6 is an introduction to logic synthesis. It starts with a description of register transfer concepts, which is followed by a description of Verilog features for specifying combinational logic. The topics covered include specification of don't-cares, latch, flip-flop, tristate inferencing, and finite state machine specification. Chapter 7 covers behavioral synthesis and extends the discussion of cycle-accurate and control specifications. It includes the concepts of always blocks, Mealy/Moore structures, and data and control path tradeoffs. Chapter 8 describes the advanced features of Verilog that allow the description of user-defined primitives, extending the 26 gate-level primitives provided by the language. The topics covered include combinational and sequential primitives. Chapter 9 introduces switch-level modeling and presents a dynamic MOS shift register example. A miniSim example provides the simulation concepts. Chapter 10 sketches two projects: modeling power dissipation and the design of a floppy disk controller. They can be developed into full-fledged design projects, requiring many aspects of Verilog. Appendix A supports the concepts presented in chapter 1. Appendices B through G summarize various aspects of Verilog and form the complete formal description of the language. All the chapters are well written, and the examples reinforce the concepts presented therein. Several exercises are provided at the end of each chapter. The included CD contains the examples, a simulator, and a logic synthesis tool. The authors have succeeded in providing a book suitable for practicing circuit design engineers and for electrical and computer engineering students.