Browse Theses

As VLSI circuits become larger and more complex, the need to improve design automation tools becomes more urgent. Interconnect effects dominate performance and power in the Deep Submicron (DSM) regime, and Computer Aided Design (CAD) tools and methodologies need to focus more on interconnect optimization. In addition, there is a push for dramatic levels of on-chip integration in modern circuits. The cumulative effects of the two make design of leading-edge electronic products difficult. In this dissertation, we propose improved techniques and methodologies for layout design of modern VLSI chips. These techniques can be classified as floor-planning, mixed-size placement and placement for physical synthesis. The proposed algorithms address novel problem formulations and design concerns that arise in DSM VLSI designs. Large macro blocks, pre-designed datapaths, embedded memories and analog blocks are increasingly used in ASIC designs. While a number of works address large-scale standard-cell placement, they often assume that all large blocks are pre-placed. Robust algorithms for large-scale placement of mixed-size designs have only recently been considered in the literature. We address the computational difficulty of layout problems involving large macros and numerous small logic cells at the same time. Macros can be handled by traditional floorplanning, but are harder to account for in min-cut and analytical placement. On the other hand, current floorplanning techniques do not scale to large numbers of objects, especially in terms of solution quality. Our work proposes to integrate min-cut placement with fixed-outline floor-planning to solve the more general placement problem, which includes cell placement, floorplanning and mixed-size placement. We study the fixed-outline floorplanning formulation that is relevant to hierarchical design style. Our contributions include new objective functions and new types of local moves for the simulated annealing based floorplanning framework, that better guide local search in the new fixed-die context. We present a new paradigm for integrating floorplanning and partitioning based placement. Our work describes a prototype CAD tool, a floorplacer, that can be used in novel VLSI design flows that unify chip floorplanning and large-scale placement. Empirically, our proposed placement framework improves the scalability and quality of results for traditional wirelength-driven floorplanning and mixed-size placement.