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Perfect-balance planar clock routing with minimal path-length

Authors:

Qing Zhu,

Wayne Wei-Ming DaiAuthors Info & Claims

ICCAD '92: Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

Pages 473 - 476

Published: 08 November 1992 Publication History

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References

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A. Kahng, j. Gong, and G. Robins. High-performance clock routing based on recursive geometric matching, in Proc. of ~Sth Design Automation Conf., pages 322-327, 1991.

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Qing Zhu and Wayne Wei-Ming Dai. Perfect-balance planar clock routing with minimal path-length. Technical Report, Computer Engineering Board of Studies, H.C. Santa Cruz, UCSG-GRL-92-12, April 1992.

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Cited By

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Charikar MKleinberg JKumar RRajagopalan SSahai ATomkins ATarjan RWarnow T(1999)Minimizing wirelength in zero and bounded skew clock treesProceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms10.5555/314500.314553(177-184)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.5555/314500.314553
Cong JKahng AKoh CTsao CRudell R(1995)Bounded-skew clock and Steiner routing under Elmore delayProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.224861(66-71)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.224861
Huang DKahng ATsao CPreas B(1995)On the bounded-skew clock and Steiner routing problemsProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217579(508-513)Online publication date: 1-Jan-1995
https://dl.acm.org/doi/10.1145/217474.217579
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Index Terms

Perfect-balance planar clock routing with minimal path-length
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Very large scale integration design

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ICCAD '96: Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Due to process, manufacturing and system operating conditions in a real environment, clock jitter is inevitable. In the presence of jitter, zero or near-zero skew are not really safe for reliable clock operations. Appropriate skew or useful skew can ...

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Information & Contributors

Information

Published In

ICCAD '92: Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design

November 1992

637 pages

ISBN:0897915402

Chairmen:
Louise Trevillyan
IBM Corp., Yorktown Heights, NY
,
Michael Lightner
Univ. of Colorado, Boulder

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 08 November 1992

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

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Charikar MKleinberg JKumar RRajagopalan SSahai ATomkins ATarjan RWarnow T(1999)Minimizing wirelength in zero and bounded skew clock treesProceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms10.5555/314500.314553(177-184)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.5555/314500.314553
Cong JKahng AKoh CTsao CRudell R(1995)Bounded-skew clock and Steiner routing under Elmore delayProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.224861(66-71)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.224861
Huang DKahng ATsao CPreas B(1995)On the bounded-skew clock and Steiner routing problemsProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217579(508-513)Online publication date: 1-Jan-1995
https://dl.acm.org/doi/10.1145/217474.217579
Vittal AMarek-Sadowska MPreas B(1995)Power optimal buffered clock tree designProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217577(497-502)Online publication date: 1-Jan-1995
https://dl.acm.org/doi/10.1145/217474.217577
Xi JDai WPreas B(1995)Buffer insertion and sizing under process variations for low power clock distributionProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217576(491-496)Online publication date: 1-Jan-1995
https://dl.acm.org/doi/10.1145/217474.217576
Tsao CKahng AMermet J(1994)Planar-DMEProceedings of the conference on European design automation10.5555/198174.198300(440-445)Online publication date: 23-Sep-1994
https://dl.acm.org/doi/10.5555/198174.198300
Seki MInoue KKato KTsurusaki KFukasawa SSasaki HAizawa MJess JRudell R(1994)A specified delay accomplishing clock router using multiple layersProceedings of the 1994 IEEE/ACM international conference on Computer-aided design10.5555/191326.191449(289-292)Online publication date: 6-Nov-1994
https://dl.acm.org/doi/10.5555/191326.191449
Lin SWong CJess JRudell R(1994)Process-variation-tolerant clock skew minimizationProceedings of the 1994 IEEE/ACM international conference on Computer-aided design10.5555/191326.191443(284-288)Online publication date: 6-Nov-1994
https://dl.acm.org/doi/10.5555/191326.191443
Kahng ATsao CJess JRudell R(1994)Low-cost single-layer clock trees with exact zero Elmore delay skewProceedings of the 1994 IEEE/ACM international conference on Computer-aided design10.5555/191326.191411(213-218)Online publication date: 6-Nov-1994
https://dl.acm.org/doi/10.5555/191326.191411
Zhu QDai WXi JLightner MJess J(1993)Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line modelsProceedings of the 1993 IEEE/ACM international conference on Computer-aided design10.5555/259794.259892(628-633)Online publication date: 7-Nov-1993
https://dl.acm.org/doi/10.5555/259794.259892

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PERFECT-BALANCE PLANAR CLOCK ROUTING WITH MINIMAL PATH LENGTH

Clock routing for low power

Jitter-tolerant clock routing in two-phase synchronous systems