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Analytic evaluation of shared-memory systems with ILP processors

Published: 16 April 1998 Publication History

Abstract

This paper develops and validates an analytical model for evaluating various types of architectural alternatives for shared-memory systems with processors that aggressively exploit instruction-level parallelism. Compared to simulation, the analytical model is many orders of magnitude faster to solve, yielding highly accurate system performance estimates in seconds.The model input parameters characterize the ability of an application to exploit instruction-level parallelism as well as the interaction between the application and the memory system architecture. A trace-driven simulation methodology is developed that allows these parameters to be generated over 100 times faster than with a detailed execution-driven simulator.Finally, this paper shows that the analytical model can be used to gain insights into application performance and to evaluate architectural design trade-offs.

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      cover image ACM Conferences
      ISCA '98: Proceedings of the 25th annual international symposium on Computer architecture
      April 1998
      402 pages
      ISBN:0818684917
      • cover image ACM SIGARCH Computer Architecture News
        ACM SIGARCH Computer Architecture News  Volume 26, Issue 3
        Special Issue: Proceedings of the 25th annual international symposium on Computer architecture (ISCA '98)
        June 1998
        379 pages
        ISSN:0163-5964
        DOI:10.1145/279361
        Issue’s Table of Contents

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      IEEE Computer Society

      United States

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      Published: 16 April 1998

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      June 27 - July 2, 1998
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      • (2016)Accurate phase-level cross-platform power and performance estimationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897977(1-6)Online publication date: 5-Jun-2016
      • (2015)ELFProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.1145/2807591.2807598(1-12)Online publication date: 15-Nov-2015
      • (2015)A Simple Model to Quantify the Impact of Memory Latency and Bandwidth on PerformanceACM SIGMETRICS Performance Evaluation Review10.1145/2796314.274590043:1(471-472)Online publication date: 15-Jun-2015
      • (2015)TransitProceedings of the 24th International Symposium on High-Performance Parallel and Distributed Computing10.1145/2749246.2749265(101-106)Online publication date: 15-Jun-2015
      • (2015)A Simple Model to Quantify the Impact of Memory Latency and Bandwidth on PerformanceProceedings of the 2015 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems10.1145/2745844.2745900(471-472)Online publication date: 15-Jun-2015
      • (2014)A queueing theoretic approach for performance evaluation of low-power multi-core embedded systemsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2013.07.00374:1(1872-1890)Online publication date: 1-Jan-2014
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