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Verifying correct pipeline implementation for microprocessors

Published: 13 November 1997 Publication History

Abstract

We introduce a general, automatic verification technique for pipelined designs. The technique is based on a scalable, formal methodology for analyzing pipelines. The key advantages to our technique are: it specifically targets pipeline control, making it more efficient; it requires no explicit specification, since it compares hardware against itself; it can be used within the broader framework of hierarchical verification; and, it can be easily extended to handle certain "complex" pipelined structures.

References

[1]
V. Bhagwati and S. Devadas, "Automatic Verification of Pipelined Microprocessors," in Proceedings of 31st Design Automation Conference, San Diego CA, June 1994.
[2]
J. R. Burch and D. L. Dill, "Automatic Verification of Pipelined Microprocessor Control," in Conference on Computer-Aided Verification, Lecture Notes in Computer Science, vol 18, pp 68-80, Springer-Verlag, 1994.
[3]
C. Barrett, D. L. Dill and J. Levitt, "Validity Checking for Combinations of Theories with Equality" in Proceedings of The International Conference on Formal Methods in Computer-Aided Design, Palo Alto, CA, November 1996.
[4]
J. R. Burch, "Techniques for Verifying Superscalar Microprocessors" in Proceedings of The 33rid ACM/IEEE Design Automation Conference, Las Vegas NV, June 1996.
[5]
J. Levitt and K. Olukotun, "A Scalable Formal Verification Methodology for Pipelined Microprocessors" in Proceedings of The 33rid ACM/IEEE Design Automation Conference, Las Vegas NV, June 1996.
[6]
J. Hennessy and D. Paterson, Computer Architecture: A Quantitative Approach, 2nd ed. Morgan Kaufman, 1996.
[7]
R. B. Jones, D. L. Dill, J. R. Burch, "Efficient Validity Checking for Processor Verification," in Proceedings of The International Conference on Computer Aided Design, San Jose CA, Nov, 1995.
[8]
M. C. McFarland, "Formal Verification of Sequential Hardware: A Tutorial," IEEE Transactions on computer- Aided Design of lntegrated Circuits and Systems, vol. 12, no. 5, May 1993.
[9]
K. McMillan, "Fitting Formal Methods into the Design Cycle," in Proceedings of 31st Design Automation Conference, San Diego CA, June, 1994.
[10]
M. Srivas and M. Bickford, "Formal Verification of a Pipelined Microprocessor" IEEE Software, vol. 7, no. 5), pp. 52-64, Sept. 1990

Cited By

View all
  • (2005)A framework for systematic validation and debugging of pipeline simulatorsACM Transactions on Design Automation of Electronic Systems10.1145/1080334.108033610:3(462-491)Online publication date: 1-Jul-2005
  • (2004)Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of MicroprocessorsProceedings of the conference on Design, automation and test in Europe - Volume 110.5555/968878.969033Online publication date: 16-Feb-2004
  • (2004)Efficient formal verification of pipelined processors with instruction queuesProceedings of the 14th ACM Great Lakes symposium on VLSI10.1145/988952.988975(92-95)Online publication date: 26-Apr-2004
  • Show More Cited By

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Published In

cover image ACM Conferences
ICCAD '97: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
November 1997
769 pages
ISBN:0818682000

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IEEE Computer Society

United States

Publication History

Published: 13 November 1997

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

View all
  • (2005)A framework for systematic validation and debugging of pipeline simulatorsACM Transactions on Design Automation of Electronic Systems10.1145/1080334.108033610:3(462-491)Online publication date: 1-Jul-2005
  • (2004)Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of MicroprocessorsProceedings of the conference on Design, automation and test in Europe - Volume 110.5555/968878.969033Online publication date: 16-Feb-2004
  • (2004)Efficient formal verification of pipelined processors with instruction queuesProceedings of the 14th ACM Great Lakes symposium on VLSI10.1145/988952.988975(92-95)Online publication date: 26-Apr-2004
  • (2004)Modeling and validation of pipeline specificationsACM Transactions on Embedded Computing Systems10.1145/972627.9726333:1(114-139)Online publication date: 1-Feb-2004
  • (2000)Si-EmulationProceedings of the 2000 IEEE International Test Conference10.5555/839295.843556Online publication date: 3-Oct-2000
  • (1999)High-level test generation for design verification of pipelined microprocessorsProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.309912(185-188)Online publication date: 1-Jun-1999
  • (1998)Formal verification of pipeline control using controlled token nets and abstract interpretationProceedings of the 1998 IEEE/ACM international conference on Computer-aided design10.1145/288548.289082(529-536)Online publication date: 1-Nov-1998

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