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A 1-V 1-Mb SRAM for portable equipment

Published: 12 August 1996 Publication History
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References

[1]
Mutoh, el al., "A 1-V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Application," ISSCC Dig. Tech. Papers, pp. 168-169, Feb. 1996.
[2]
Izumikawa, el al., "A 0.9-V 100-MI-Iz 4-roW 2-ram2 16-b DSP Core," ISSCC Dig. Tech. Papers, pp. 84-85, Feb. 1995.
[3]
Date, el al., "I-V 30-MI-Iz Memory-Macrocell-Circuit Technology with a 0.5-#m Multi-threshold CMOS," IEEE Symp. on Low Power Electronics Dig. Tech. Papers, pp. 90-91, Sept. 1994.
[4]
Mizuno, el al., "A 1-V 100-MI-Iz 10-roW Cache using Separated Bit-Line Memory Hierarchy and Domino Tag Comparators," ISSCC Dig. Tech. Papers, pp. 152-153, " Feb. 1996.
[5]
Takashima, el al., "Standby/active Mode Logic for Sub-lV Operating ULSI Memory" IEEE J. Solid-State Circuits, vol. 29, no. 4, pp. 441-447, Apr. 1994.

Cited By

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  • (1998)Energy-delay efficient data storage and transfer architecturesProceedings of the conference on Design, automation and test in Europe10.5555/368058.368343(709-715)Online publication date: 23-Feb-1998

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cover image ACM Conferences
ISLPED '96: Proceedings of the 1996 international symposium on Low power electronics and design
August 1996
390 pages

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IEEE Press

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Published: 12 August 1996

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  • (1998)Energy-delay efficient data storage and transfer architecturesProceedings of the conference on Design, automation and test in Europe10.5555/368058.368343(709-715)Online publication date: 23-Feb-1998

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