Article

Free access

Single-layer fanout routing and routability analysis for Ball Grid Arrays

Authors:

Man-Fai Yu,

Wayne Wei-Ming DaiAuthors Info & Claims

ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Pages 581 - 586

Published: 01 December 1995 Publication History

PDF eReader Publisher Site

Abstract

Fanout routing for Ball Grid Array(BGA) packages becomes non-trivial when the I/O pin count increases. When the number of I/Os gets larger and larger, the number of I/Os we can put on a package may not limited by the available area but sometimes by the ability to fan them out on the next level of interconnect---the PCB or MCM substrate. This paper presents an efficient algorithm (EVENFANOUT) which generates the optimal uniform distribution of wires. We have found the three cuts that is decisive on the routability of the package using EVENFANOUT. These decisive cuts form the base for design optimization of the package.

References

[1]

J. Darnauer and W. W.-M. Dai, "Fast pad redistribution from periphery-io to area-io," in Proc. IEEE Multi-Chip Module Conf., (Santa Cruz, CA), pp. 38- 43, March 1994.

Google Scholar

[2]

M.-F. Yu and W. W.-M. Dai, "Pin assignment and routing on a single-layer pin grid array," Tech Report UCSC-CRL-95-15, University of California, Santa Cruz, 1995.

Digital Library

Google Scholar

[3]

W. W.-M. Dai, T. Dayan, and D. Staepelaere, "Topological routing in surf: Generating a rubber-band sketch," in Proc. 28th Design Automation Conf., (Anaheim, CA), pp. 39-44, IEEE Computer Society Press, 1991.

Digital Library

Google Scholar

[4]

W. W.-M. Dai, R. Kong, and M. Sato, "Routability of a rubber-band sketch," in Proc. 28th Design Automation Conf., (Anaheim, CA), pp. 45-48, IEEE Computer Society Press, 1991.

Digital Library

Google Scholar

[5]

W. W.-M. Dai, R. Kong, J. Jue, and M. Sato, "Rubber band routing and dynamic data representation," in Proc. 1990 Int'l Conf. on CAD, (San Jose, CA), pp. 52-55, IEEE Computer Society, November 1990.

Google Scholar

[6]

D. Staepelaere, J. Jue, T. Dayan, and W. W.-M. Dai, "Surf:a rubber-band routing system for multichip modules," IEEE Design and Test Magazine, December 1993.

Digital Library

Google Scholar

Cited By

View all

Ahmadinejad AZarrabi-Zadeh H(2017)Finding Maximum Disjoint Set of Boundary Rectangles With Application to PCB RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.258576136:3(412-420)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2585761
Wang KWang HDong SKoh CSze C(2013)Escape routing of mixed-pattern signals based on staggered-pin-array PCBsProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451941(93-100)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451941
Lee RChen H(2013)A study of row-based area-array I/O design planning in concurrent chip-package design flowACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210118:2(1-19)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442101
Show More Cited By

Index Terms

Single-layer fanout routing and routability analysis for Ball Grid Arrays
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

Recommendations

Routability-Driven Blockage-Aware Macro Placement
DAC '14: Proceedings of the 51st Annual Design Automation Conference

We present a new floorplan representation, called circular-packing trees (CP-trees), for the problem of macro placement. Our CP-trees can flexibly pack movable macros toward corners or pre-placed macros along chip boundaries circularly to optimize macro ...
A global routing method for 2-layer ball grid array packages
ISPD '05: Proceedings of the 2005 international symposium on Physical design

In current VLSI circuits, there can be hundreds of required I/O pins. BGA(Ball Grid Array) packaging is commonly used to realize the huge number of connections between VLSI and PCB. In this paper, we propose a global routing method for two-layer BGA ...
SINGLE-LAYER FANOUT ROUTING AND ROUTABILITY ANALYSIS FOR BALL GRID ARRAYS

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

December 1995

748 pages

ISBN:0818672137

Chairman:
Richard Rudell
Synopsys, Inc., Mountain View, CA

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 December 1995

Check for updates

Author Tags

Qualifiers

Article

Conference

ICCAD '95

Sponsor:

SIGDA
IEEE-CS

ICCAD '95: International Conference on Computer Aided Design

November 5 - 9, 1995

California, San Jose, USA

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

22
Total Citations
View Citations
273
Total Downloads

Downloads (Last 12 months)16
Downloads (Last 6 weeks)6

Reflects downloads up to 19 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Ahmadinejad AZarrabi-Zadeh H(2017)Finding Maximum Disjoint Set of Boundary Rectangles With Application to PCB RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.258576136:3(412-420)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2585761
Wang KWang HDong SKoh CSze C(2013)Escape routing of mixed-pattern signals based on staggered-pin-array PCBsProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451941(93-100)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451941
Lee RChen H(2013)A study of row-based area-array I/O design planning in concurrent chip-package design flowACM Transactions on Design Automation of Electronic Systems10.1145/2442087.244210118:2(1-19)Online publication date: 11-Apr-2013
https://dl.acm.org/doi/10.1145/2442087.2442101
Yan TWu PMa QWong MScheffer LPhillips JHu A(2010)On the escape routing of differential pairsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133559(614-620)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133559
Yan TWong MScheffer LPhillips JHu A(2010)Recent research development in PCB layoutProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133514(398-403)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133514
Kong HMa QYan TWong MSapatnekar S(2010)An optimal algorithm for finding disjoint rectangles and its application to PCB routingProceedings of the 47th Design Automation Conference10.1145/1837274.1837326(212-217)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837326
Luo LYan TMa QWong MShibuya TSaxena PChang Y(2010)B-escapeProceedings of the 19th international symposium on Physical design10.1145/1735023.1735033(19-25)Online publication date: 14-Mar-2010
https://dl.acm.org/doi/10.1145/1735023.1735033
Lu CChen HLiu CShih WBenini LDe Micheli GAl-Hashimi BMueller W(2009)Package routability- and IR-drop-aware finger/pad assignment in chip-package co-designProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874826(845-850)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874826
Yan TWong M(2009)A correct network flow model for escape routingProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630001(332-335)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630001
Lee RChen H(2009)Fast flip-chip pin-out designation respin for package-board codesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201779517:8(1087-1098)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TVLSI.2009.2017795
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Routability-Driven Blockage-Aware Macro Placement

A global routing method for 2-layer ball grid array packages

SINGLE-LAYER FANOUT ROUTING AND ROUTABILITY ANALYSIS FOR BALL GRID ARRAYS