Article

Free access

Stable and efficient reduction of substrate model networks using congruence transforms

Authors:

Kevin J. Kerns,

Ivan L. Wemple,

Andrew T. YangAuthors Info & Claims

ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Pages 207 - 214

Published: 01 December 1995 Publication History

PDF eReader Publisher Site

Abstract

Parasitic analog-digital noise coupling has been identified as a key issue facing designers of mixed-signal integrated circuits. In particular, signal cross talk through the common chip substrate has become increasingly problematic. This paper demonstrates a new methodology for developing simulation, synthesis, and verification models to analyze the global electrical behavior of the non-ideal semiconductor substrate. RC substrate network models, which are generated via a triangular discretization method, are accurately approximated for subsequent analysis by an efficient reduction algorithm. This algorithm utilizes the well-conditioned Lanczos process to formulate Pade approximations of the network port admittance. Congruence transformations are employed to ensure stability, and to create reduced networks which are easily realizable with SPICE-compatible RC elements. For validation, the strategy has been successfully applied to several mixed-signal circuit examples.

References

[1]

J.A. Olmstead and S. Vulih, "Noise problems in mixed analog-digital integrated circuits", Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 659-662, 1987.

Google Scholar

[2]

S. Kumashiro, R.A. Rohrer, and A.J. Strojwas, "A new efficient method for the transient simulation of three-dimensional interconnect structures", Proceedings of the IEEE International Electron Devices Meeting, pp. 193-196, 1990.

Crossref

Google Scholar

[3]

L.T. Pillage and R.A. Rohrer, "Asymptotic waveform evaluation for timing analysis", IEEE Transactions on Computer-Aided Design, vol. 9, no. 4, pp. 352-366, April 1990.

Crossref

Google Scholar

[4]

N.K. Verghese, D.J. Allstot, and S. Masui, "Rapid simulation of substrate coupling effects in mixed-mode ICs", Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 18.3.1-18.3.4, 1993.

Crossref

Google Scholar

[5]

V. Raghavan, R.A. Rohrer, L.T. Pillage, J.Y. Lee, J.E. Bracken, and M.M. Alaybeyi, "AWE-inspired," Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 18.1.3-18.1.8, 1993.

Google Scholar

[6]

T.A. Johnson, R.W. Knepper, V. Marcello, and W. Wang, "Chip substrate resistance modeling technique for integrated circuit design", IEEE Transactions on Computer-Aided Design, vol. CAD-3, no. 2, pp. 126-134, April 1984.

Google Scholar

[7]

S. Fortune, "A sweepline algorithm for Voronoi diagrams", Algorithmica, 2, pp. 153-174, 1987.

Digital Library

Google Scholar

[8]

I.L. Wemple and A.T. Yang, "Mixed-signal switching noise analysis using Voronoi-tessellated substrate macromodels", Proceedings of the 32nd ACM/IEEE Design Automation Conference, pp. 439-444, 1995.

Digital Library

Google Scholar

[9]

E Feldmann and R.W. Freund, "Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm", Proceedings of the 32nd ACM/IEEE Design Automation Conference, pp. 474-479, 1995.

Digital Library

Google Scholar

[10]

A. George and J.W.-H. Liu, Computer Solution of Large Sparse Positive Definite Systems, Prentice-Hall, Englewood Cliffs, NJ, 1981.

Digital Library

Google Scholar

[11]

G.H. Golub and C.F. Van Loan, Matrix Computations, second edition, Johns Hopkins University Press, Baltimore, MD, 1993.

Google Scholar

[12]

M.R. Wohlers, Lumped and Distributed Passive Networks: A Generalized and Advanced Viewpoint, Academic Press, New York, NY, 1969.

Google Scholar

[13]

HSPICE, Meta-Software, Inc., Version H95.1, Campbell, CA, 1995.

Google Scholar

[14]

K.S. Kundert and A. Sangiovanni-Vincentelli, User's Guide for Sparse: A Sparse Linear Equation Solver, Version 1.3a, Department of EECS, University of California, Berkeley, CA, 1988.

Google Scholar

Cited By

View all

Karthik ARoychowdhury J(2013)ABCD-LProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488811(1-9)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488811
Zhang ZWang QWong NDaniel L(2011)A moment-matching scheme for the passivity-preserving model order reduction of indefinite descriptor systems with possible polynomial partsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950824(49-54)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950824
Bond BDaniel L(2009)Stable reduced models for nonlinear descriptor systems through piecewise-linear approximation and projectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203059628:10(1467-1480)Online publication date: 1-Oct-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2030596
Show More Cited By

Index Terms

Stable and efficient reduction of substrate model networks using congruence transforms
1. Applied computing
  1. Physical sciences and engineering
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

Recommendations

Exact closed-form expressions for substrate resistance and capacitance extraction in nanoscale VLSI

A new exact formula to determine the substrate resistance and capacitance is presented in this work. It is derived from the solution of the Laplace equations for equivalent problems. It achieves the level of accuracy of standard electromagnetic methods ...
Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies
ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

This paper demonstrates viable device design options for low-leakage and robust SRAM in sub-50nm FD/SOI technology. We explore the possibilities of reducing the body-doping of FD/SOI devices with proper tuning of back-gate bias or gate workfunction to ...
A green function-based parasitic extraction method for inhomogeneous substrate layers
DAC '05: Proceedings of the 42nd annual Design Automation Conference

This paper presents a new Green function-based approach for substrate parasitic extraction in substrates with inhomogeneous layers. This new formulation allows analysis of noise coupling with sinkers, trenches and wells, - a limitation in prior Green ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

December 1995

748 pages

ISBN:0818672137

Chairman:
Richard Rudell
Synopsys, Inc., Mountain View, CA

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 December 1995

Check for updates

Author Tags

Qualifiers

Article

Conference

ICCAD '95

Sponsor:

SIGDA
IEEE-CS

ICCAD '95: International Conference on Computer Aided Design

November 5 - 9, 1995

California, San Jose, USA

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

40
Total Citations
View Citations
312
Total Downloads

Downloads (Last 12 months)28
Downloads (Last 6 weeks)12

Reflects downloads up to 19 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Karthik ARoychowdhury J(2013)ABCD-LProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488811(1-9)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488811
Zhang ZWang QWong NDaniel L(2011)A moment-matching scheme for the passivity-preserving model order reduction of indefinite descriptor systems with possible polynomial partsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950824(49-54)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950824
Bond BDaniel L(2009)Stable reduced models for nonlinear descriptor systems through piecewise-linear approximation and projectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203059628:10(1467-1480)Online publication date: 1-Oct-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2030596
Bond BDaniel LNassif SRoychowdhury J(2008)Guaranteed stable projection-based model reduction for indefinite and unstable linear systemsProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509615(728-735)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509615
Li ZShi CHirose F(2006)A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplingsProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118399(402-407)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118399
Sheehan B(2003)Branch Merge Reduction of RLCM NetworksProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009959Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009959
Qin ZCheng CGetreu IFix LLavagno L(2003)Realizable parasitic reduction using generalized Y-Δ transformationProceedings of the 40th annual Design Automation Conference10.1145/775832.775890(220-225)Online publication date: 2-Jun-2003
https://dl.acm.org/doi/10.1145/775832.775890
Qin ZCheng CYasuura H(2003)RCLK-VJ network reduction with Hurwitz polynomial approximationProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119827(283-291)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119827
Kim KJung SKim TSaxena PLiu CKang S(2003)Coupling delay optimization by temporal decorrelation using dual threshold voltage techniqueIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81711111:5(879-887)Online publication date: 1-Oct-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.817111
Schrik EDewilde Pvan der Meijs NPileggi LKuehlmann A(2002)Theoretical and practical validation of combined BEM/FEM substrate resistance modelingProceedings of the 2002 IEEE/ACM international conference on Computer-aided design10.1145/774572.774574(10-15)Online publication date: 10-Nov-2002
https://dl.acm.org/doi/10.1145/774572.774574
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Exact closed-form expressions for substrate resistance and capacitance extraction in nanoscale VLSI

Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies

A green function-based parasitic extraction method for inhomogeneous substrate layers