research-article

A design flow dedicated to multi-mode architectures for DSP applications

Authors:

Cyrille Chavet,

Caaliph Andriamisaina,

Philippe Coussy,

Emmanuel Casseau,

Eric MartinAuthors Info & Claims

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Pages 604 - 611

Published: 05 November 2007 Publication History

Abstract

This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis tool, named GAUT. Given a unified description of a set of time-wise mutually exclusive tasks and their associated throughput constraints, a single RTL hardware architecture optimized in area is generated. In order to reduce the register, steering logic (multiplexers) and controller (decoding logic) complexities, we propose a joint-scheduling algorithm which maximizes the similarities between control steps and specific binding approaches for both functional units and storage elements which maximize the similarities between the datapaths. We show through a set of test cases that our approach offers significant area saving relative to the state-of-the-art.

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Cited By

Bian SShintani MMorita SAwano HHiromoto MSato TCoskun AMargala MBehjat LHan J(2016)Workload-Aware Worst Path Analysis of Processor-Scale NBTI DegradationProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903013(203-208)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2903013
Al Farisi BHeyse KBruneel KCardoso JStroobandt D(2015)Enabling FPGA routing configuration sharing in dynamic partial reconfigurationDesign Automation for Embedded Systems10.1007/s10617-014-9143-819:1-2(189-221)Online publication date: 1-Mar-2015
https://dl.acm.org/doi/10.1007/s10617-014-9143-8
Ben-Asher YRotem N(2013)The benefits of using variable-length pipelined operations in high-level synthesisACM Transactions on Embedded Computing Systems10.1145/2539036.253904813:3(1-23)Online publication date: 24-Dec-2013
https://dl.acm.org/doi/10.1145/2539036.2539048
Show More Cited By

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Information & Contributors

Information

Published In

cover image ACM Conferences

ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

November 2007

933 pages

ISBN:1424413826

General Chair:
Georges Gielen
ESAT-MICAS, Katholieke Univ. Leuven, Leuven, Belgium

Sponsors

CEDA: Council on Electronic Design Automation
SIGDA: ACM Special Interest Group on Design Automation
IEEE CASS/CANDE
IEEE-CS\DATC: IEEE Computer Society

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IEEE Press

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Published: 05 November 2007

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Research-article

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ICCAD07

Sponsor:

CEDA
SIGDA
IEEE-CS\DATC

ICCAD07: The International Conference on Computer-Aided Design 2007

November 5 - 8, 2007

California, San Jose

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ICCAD '07 Paper Acceptance Rate 139 of 510 submissions, 27%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Bian SShintani MMorita SAwano HHiromoto MSato TCoskun AMargala MBehjat LHan J(2016)Workload-Aware Worst Path Analysis of Processor-Scale NBTI DegradationProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903013(203-208)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2903013
Al Farisi BHeyse KBruneel KCardoso JStroobandt D(2015)Enabling FPGA routing configuration sharing in dynamic partial reconfigurationDesign Automation for Embedded Systems10.1007/s10617-014-9143-819:1-2(189-221)Online publication date: 1-Mar-2015
https://dl.acm.org/doi/10.1007/s10617-014-9143-8
Ben-Asher YRotem N(2013)The benefits of using variable-length pipelined operations in high-level synthesisACM Transactions on Embedded Computing Systems10.1145/2539036.253904813:3(1-23)Online publication date: 24-Dec-2013
https://dl.acm.org/doi/10.1145/2539036.2539048
York JChiou DGroeneveld PSciuto DHassoun S(2012)On the asymptotic costs of multiplexer-based reconfigurabilityProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228503(790-795)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228503
Andriamisaina CCoussy PCasseau EChavet C(2010)High-level synthesis for designing multimode architecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.206275129:11(1736-1749)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2062751
Ben-Asher YRotem NShochat E(2010)Finding the best compromise in compiling compound loops to VerilogJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2010.07.00156:9(474-486)Online publication date: 1-Sep-2010
https://dl.acm.org/doi/10.1016/j.sysarc.2010.07.001
Fazlali MFallah MZolghadr MZakerolhosseini A(2009)A New Datapath Merging Method for Reconfigurable SystemProceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications10.1007/978-3-642-00641-8_17(157-168)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1007/978-3-642-00641-8_17

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