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Task scheduling for reliable cache architectures of multiprocessor systems

Published: 16 April 2007 Publication History

Abstract

This paper presents a task scheduling method for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of vulnerable SRAMs under real-time constraints. A mixed integer programming model has been built for minimizing vulnerability under real-time constraints. Experimental results have shown that our task scheduling method achieved 47.7--99.9% less vulnerability than a conventional approach.

References

[1]
P. Elakkumanan, K. Prasad, and R. Sridhar, "Time redundancy based scan flip-flop reuse to reduce SER of combinational logic," Proc. IEEE International Symposium on Quality Electronic Design (ISQED), pp. 617--622, March 2006.
[2]
M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge and R. B. Brown, "MiBench: A Free, commercially representative embedded benchmark suite," Proc. IEEE Workshop on Workload Characterization, December 2001.
[3]
J. L. Hennessy and D. A. Patterson, "Computer architecture: a quantitative approach," pp. 401--402, Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2002.
[4]
N. Seifert, D. Moyer, N. Leland and R. Hokinson, "Historical trend in alpha-particle induced soft error rates of the Alpha(tm) microprocessor," Proc. IEEE International Reliability Physics Symposium (IRPS), pp. 259--265, April 2001.
[5]
N. Seifert, X. Zhu, D. Moyer, R. Mueller, R. Hokinson, N. Leland, M. Shade, and L. Massengill, "Frequency dependence of soft error rates for sub-micron CMOS technologies," in the Technical Digest of International Electron Devices Meeting (IEDM), pp. 14.4.1--14.4.4, December 2001.
[6]
T. Karnik, B. Bloechel, K. Soumyanath, V. De and S. Borkar, "Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18°," Proc. Symposium on VLSI Circuits, pp. 61--62, June 2001.
[7]
H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, "Vulnerability analysis of L2 cache elements to single event upsets," Proc. Design, Automation and Test in Europe Conference (DATE), pp. 1276--1281, March 2006.
[8]
A. Biswas, P. Racunas, R. Cheveresan, J. Emer, S. S. Mukherjee, and R. Rangan, "Computing architectural vulnerability factors for address-based structures," Proc. IEEE International Symposium on Computer Architecture (ISCA), pp. 532--543, June 2005.
[9]
X. Li, S. V. Adve, P. Bose, and J. A. Rivers, "SoftArch: An architecture level tool for modeling and analyzing soft errors," Proc. IEEE International Conference on Dependable Systems and Networks (DSN), pp. 496--505, June 2005.
[10]
M. Sugihara, T. Ishihara, K. Hashimoto, and M. Muroyama, "A simulation-based soft error estimation methodology for computer systems," Proc. IEEE International Symposium on Quality Electronic Design (ISQED), pp. 196--203, March 2006.
[11]
M. Sugihara, T. Ishihara, and K. Murakami, "An analysis on a tradeoff between reliability and performance and a reliable cache architecture for computer systems," IEICE Technical Report, SIP2006--99, pp. 93--98, October 2006.
[12]
M. Sugihara, T. Ishihara, and K. Murakami, "A task scheduling method for reliable cache architectures," IEICE Technical Report, CPSY2006--34, pp. 1--6, November 2006.
[13]
C. W. Slayman, "Cache and memory error detection, correction and reduction techniques for terrestrial servers and workstations," IEEE T-DMR, 5(3):397--404, 2005.
[14]
H. P. Williams, Model Building in Mathematical Programming, John Wiley & Sons, 1999.
[15]
ILOG Inc., CPLEX 9.1 Reference Manual, 2005.

Cited By

View all
  • (2016)A Survey of Techniques for Modeling and Improving Reliability of Computing SystemsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2015.242617927:4(1226-1238)Online publication date: 1-Apr-2016
  • (2010)Partitioning techniques for partially protected caches in resource-constrained embedded systemsACM Transactions on Design Automation of Electronic Systems10.1145/1835420.183542315:4(1-30)Online publication date: 7-Oct-2010

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cover image ACM Conferences
DATE '07: Proceedings of the conference on Design, automation and test in Europe
April 2007
1741 pages
ISBN:9783981080124

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EDA Consortium

San Jose, CA, United States

Publication History

Published: 16 April 2007

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DATE07
Sponsor:
  • EDAA
  • SIGDA
  • The Russian Academy of Sciences
DATE07: Design, Automation and Test in Europe
April 16 - 20, 2007
Nice, France

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2016)A Survey of Techniques for Modeling and Improving Reliability of Computing SystemsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2015.242617927:4(1226-1238)Online publication date: 1-Apr-2016
  • (2010)Partitioning techniques for partially protected caches in resource-constrained embedded systemsACM Transactions on Design Automation of Electronic Systems10.1145/1835420.183542315:4(1-30)Online publication date: 7-Oct-2010

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