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- research-articleDecember 2023
Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra
- Anchit Arun,
- Ananya Chakraborty,
- Priyanka Dutta,
- Debajyoti Pal,
- Tridibesh Nag,
- Debasis De,
- Sudip Ghosh,
- Hafizur Rahaman
IAIT '23: Proceedings of the 13th International Conference on Advances in Information TechnologyArticle No.: 23, Pages 1–6https://doi.org/10.1145/3628454.3631153In most implementations of digital circuitry, multiplication requires the highest latency and computational complexity. Vedic calculations are an ancient system of mathematics that involves mathematical computations to ascertain the multiplication in ...
- research-articleDecember 2023
Hardware Performance Analysis of N-bit CLA on FPGA and Programmable SoC
IAIT '23: Proceedings of the 13th International Conference on Advances in Information TechnologyArticle No.: 1, Pages 1–7https://doi.org/10.1145/3628454.3628455Carry Look Ahead Adders (CLA) minimize duration opposed with various adders through transmitting carry preceding the total output, which leads to better results. They increase efficiency by lowering the duration it takes to figure out carry bits. In ...
- research-articleOctober 2022
Frequency-scaled thermal-aware test scheduling for 3D ICs using machine learning based temperature estimation
AbstractThree-dimensional Integrated Circuits (3D IC) are being looked at as an alternative in overcoming some critical challenges plaguing conventional 2D ICs. However, it faces some new challenges — some of them being thermal management and ...
- research-articleMay 2022
Multi-source data fusion technique for parametric fault diagnosis in analog circuits
Integration, the VLSI Journal (INTG), Volume 84, Issue CPages 92–101https://doi.org/10.1016/j.vlsi.2022.01.005AbstractInput test signal plays important role in testing of analog circuits. Single type of input stimulus cannot maximally reveal the state of the circuit. To combat this shortcoming, this work proposes to integrate information from the ...
Highlights- This work proposes to integrate information from the output responses corresponding to different input stimuli to improve the accuracy of fault diagnosis.
- research-articleFebruary 2022
An improved synthesis technique for optical circuits using MIG and XMG
AbstractThe progress of fabrication technology in the photonics industry has achieved a significant milestone due to the practicability of performing functional computations on-chips using ultra-high-speed optical devices and low-power ...
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- research-articleFebruary 2022
Hardware Design with Real-Time Implementation for Security of Medical Images and EPMR
Circuits, Systems, and Signal Processing (CSSP), Volume 41, Issue 2Pages 867–891https://doi.org/10.1007/s00034-021-01807-5AbstractIn this article, an FPGA-based hardware prototype design has been proposed and implemented in real time for the security of the Electronic Patient Medical Record. This proposed hardware can be integrated into various medical image scanning ...
- research-articleNovember 2021
BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)
Integration, the VLSI Journal (INTG), Volume 81, Issue CPages 254–267https://doi.org/10.1016/j.vlsi.2021.08.002AbstractIn-Memory computation has received considerable attention in the light of recent advances made in the memristor-based design. Non-volatile memristor devices are compatible with both the crossbar structure, CMOS technology, and can ...
Highlights- In this work, at first, an optimized gate-level design of 2:1 multiplexer (MUX) is presented. Thereafter, the MAGIC family is used to implement the optimized ...
- research-articleJuly 2021
Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique for Intelligent Cross-Contamination Avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 29, Issue 7Pages 1451–1464https://doi.org/10.1109/TVLSI.2021.3071410Recent advances in microfluidics and microfabrication technology enabled the emergence of a new microelectrode-dot-array (MEDA) architecture for microfluidic biochips. The MEDA-based design allows dynamic routing with variable-sized droplets. The cross ...
- research-articleMay 2021
A Statistical Approach of Analog Circuit Fault Detection Utilizing Kolmogorov–Smirnov Test Method
Circuits, Systems, and Signal Processing (CSSP), Volume 40, Issue 5Pages 2091–2113https://doi.org/10.1007/s00034-020-01572-xAbstractThis work presents a testing technique based on ‘Kolmogorov–Smirnov’ (K–S) test for detection of parametric faults in analog circuits. The proposed method is a time-domain signal processing technique that compares the statistical similarity in ...
- research-articleMarch 2021
MEDA Based Biochips: Detection, Prevention and Rectification Techniques for Cyberphysical Attacks
IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB), Volume 19, Issue 4Pages 2345–2355https://doi.org/10.1109/TCBB.2021.3069380Recent advances of microelectrode-dot-array (MEDA) based Biochips have revolutionized the application of Lab-on-chip devices. New techniques for MEDA based biochips confide on the concepts on computer-aided design automation and cyberphysical integration ...
- research-articleFebruary 2021
The effect of the stacking arrangement on the device behavior of bilayer MoS2 FETs
Journal of Computational Electronics (SPJCE), Volume 20, Issue 1Pages 161–168https://doi.org/10.1007/s10825-020-01636-wAbstractThe effect of three different interlayer stacking arrangements of bilayer (BL) molybdenum disulfide (MoS2) channel material on the device behavior of p- and n-metal–oxide–semiconductor field-effect transistors (MOSFETs) is extensively investigated ...
- ArticleNovember 2020
Time-Layered Gamic Interaction with a Virtual Museum Template
Digital Heritage. Progress in Cultural Heritage: Documentation, Preservation, and ProtectionPages 311–322https://doi.org/10.1007/978-3-030-73043-7_26AbstractThis paper discusses a simplified workflow and interactive learning opportunities for exporting map and location data using a free tool, Recogito into a Unity game environment with a simple virtual museum room template. The aim was to create ...
- research-articleSeptember 2020
Analog Circuit Fault Detection by Impulse Response-Based Signature Analysis
Circuits, Systems, and Signal Processing (CSSP), Volume 39, Issue 9Pages 4281–4296https://doi.org/10.1007/s00034-020-01375-0AbstractThis paper presents a method for the detection of parametric faults in linear filters with the help of impulse response which is studied on the basis of cross-correlation, a statistical metric. Impulse input is generated with delay flip flops and ...
- research-articleJuly 2020
Bio-inspired Routing in DMFB: An Artificial Swarm Propagation Based Application
IAIT '20: Proceedings of the 11th International Conference on Advances in Information TechnologyArticle No.: 37, Pages 1–11https://doi.org/10.1145/3406601.3406642Digital Microfluidic Biochips (DMFB) has been evolved as a new generation of Lab-on-Chip device. This appears as a viable alternative to conventional benchtop laboratory process in the fields of point of care diagnostics, environmental toxicity ...
- research-articleJuly 2020
Chip level design in MEDA based biochips: application of daisy chain based actuation
Microsystem Technologies (MITE), Volume 26, Issue 7Pages 2337–2351https://doi.org/10.1007/s00542-020-04811-yAbstractRecent advances in microfluidics and micro-fabrication technology enabled the emergence of a new microelectrode-dot-array (MEDA) architecture for microfluidic biochips. The MEDA based design facilitates dynamic routing with variable sized droplets ...
- research-articleJune 2020
Function-mapping on defective nano-crossbars with enhanced reliability
Journal of Computational Electronics (SPJCE), Volume 19, Issue 2Pages 555–564https://doi.org/10.1007/s10825-020-01467-9AbstractSeveral nanoscale devices now represent viable options to replace conventional complementary metal–oxide–semiconductor (CMOS)-based designs. The problem of logic synthesis using a nanoscale two-dimensional (2D) crossbar-switch architecture is ...
- research-articleOctober 2019
A High-performance Homogeneous Droplet Routing Technique for MEDA-based Biochips
ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 15, Issue 4Article No.: 38, Pages 1–37https://doi.org/10.1145/3327965Recent advancement of microelectrode-dot-array (MEDA)-based architecture for digital microfluidic biochips has enabled a major enhancement in microfluidic operations for traditional lab-on-chip devices. One critical issue for MEDA-based biochips is the ...
- research-articleOctober 2019
Error-Oblivious Sample Preparation With Digital Microfluidic Lab-on-Chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 38, Issue 10Pages 1886–1899https://doi.org/10.1109/TCAD.2018.2864263Microfluidic chips are now being increasingly used for fast and cost-effective implementation of biochemical protocols. Sample preparation involves dilution and mixing of fluids in certain ratios, which are needed for most of the protocols. On a digital ...
- research-articleMay 2019
Fast locking, startup-circuit free, low area, 32-phase analog DLL
Integration, the VLSI Journal (INTG), Volume 66, Issue CPages 60–66https://doi.org/10.1016/j.vlsi.2019.01.003AbstractThis work presents 32-phase analog delay-locked-loop (DLL) having fast locking ability, startup-circuit free operation, and a low area with improved DNL-INL performance. The proposed faster delay-cell and the new bias-circuit enable ...
Highlights- 32-phase Analog Delay Lock Loop (DLL) features.The DLL locks in less than 54 or 56 clock ...
- research-articleMay 2019
In-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC)
- Anindita Chakraborty,
- Vivek Saurabh,
- Partha Sarathi Gupta,
- Rituraj Kumar,
- Saikat Majumdar,
- Smriti Das,
- Hafizur Rahaman
Integration, the VLSI Journal (INTG), Volume 66, Issue CPages 24–34https://doi.org/10.1016/j.vlsi.2018.12.005Abstract‘Computations inside Memory’ has become a latest area of research as ‘memory with computing skills’ accelerates the chances of developing ‘beyond-Von Neumann machines’, that is believed to be advantageous in terms of performance and ...
Highlights- In this work pure memristive-designs for two most commonly used logic blocks Delay (D) and Toggle (T) flip-flops using Memristor Aided LoGIC (MAGIC) design ...