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- research-articleNovember 2006
An efficient heuristic approach to solve the unate covering problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 20, Issue 12Pages 1377–1388https://doi.org/10.1109/43.969431The paper presents a new approach to solve the unate covering problem based on exploitation of information provided by Lagrangean relaxation. In particular, main advantages of the proposed heuristic algorithm are the effective choice of elements to be ...
- research-articleNovember 2006
Symbolic optimization of interacting controllers based on redundancy identification and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 19, Issue 7Pages 760–772https://doi.org/10.1109/43.851991This paper presents a binary decision diagram (BDD)-based algorithm for the optimization of the driven machine, M2, of a finite-state machine (FSM) network with cascade connection, M1 →M2. The technique we propose relies on redundant faults ...
- research-articleJune 1994
ALADIN: a multilevel testability analyzer for VLSI system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 2, Issue 2Pages 157–171https://doi.org/10.1109/92.285743In order to cope with tomorrow's challenges in the microelectronic market, the reliability of the first phases of the design process must be improved. The possibility of applying techniques for testability analysis at these abstract design levels can ...