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Testing functional faults in VLSI

Authors:

Yinghua Min,

Stephen Y.H. SuAuthors Info & Claims

DAC '82: Proceedings of the 19th Design Automation Conference

Pages 384 - 392

Published: 01 January 1982 Publication History

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Abstract

Functional testing has become increasingly important due to the advent of VLSI technology. This paper presents a systematic procedure for generating tests for detecting functional faults in digital systems described by the register transfer language. Procedures for testing register decoding, instruction decoding, data transfer, data storage and data manipulation function faults in microprocessors are described step-by-step. Examples are given to illustrate the procedures.

References

[1]

S.Y.H. Su and Y.I. Hsieh; "Testing Functional Faults in Digital Systems Described by Register Transfer Language," Digest of papers, 1981 Test Conference, pp. 447-457. Revised version published in Journal of Digital Systems, June 1982.

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[2]

S.M. Thatte and J.A. Abraham, "Test Generation for Microprocessors," IEEE Transactions on Computers, pp. 429-441, June 1980.

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[3]

J.A. Abraham and S.M. Thatte, "Fault Coverage of Test Programs for a Microprocessor," Digest of Papers, 1979 Test Conference, pp. 18-22.

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[4]

S.Y.H. Su, "A Survey of Computer Hardware Description Languages in the U.S.A.," Computer, Dec. 1974, pp. 45-51.

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[5]

Intel 8080 Microprocessor Systems User's Manual, Intel Corporation, Santa Clara, California, September 1975.

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[6]

S.M. Thatte and J.A. Abraham, "A Methodology for Functional Level Testing of Microprocessors," Digest of Papers FTCS-8, 1978, pp. 90-95.

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[7]

M. Karpovsky and S.Y.H. Su, "Detecting Bridging and Stuck-at Faults at Input and Output Pins of Standard Digital Components," Proceedings of 17th Design Automation Conference, pp. 494-505, June 1980.

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[8]

M. Karpovsky and S.Y.H. Su, "Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines," IEEE Transactions on Computers, pp. 523-527, June 1980.

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Cited By

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Shen JAbraham J(1998)Native mode functional test generation for processors with applications to self test and design validationProceedings of the 1998 IEEE International Test Conference10.5555/648020.745609(990-999)Online publication date: 18-Oct-1998
https://dl.acm.org/doi/10.5555/648020.745609
Vandeventer LSantucci JMermet J(1994)Algorithms for behavioral test pattern generation from VHDL circuit descriptions containing loop language constructsProceedings of the conference on European design automation10.5555/198174.198344(638-643)Online publication date: 23-Sep-1994
https://dl.acm.org/doi/10.5555/198174.198344
Vandeventer LSantucci JMermet J(1994)Speeding up test pattern generation from behavioral VHDL descriptions containing several processesProceedings of the conference on European design automation10.5555/198174.198343(632-637)Online publication date: 23-Sep-1994
https://dl.acm.org/doi/10.5555/198174.198343
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Index Terms

Testing functional faults in VLSI
1. Hardware

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Published In

DAC '82: Proceedings of the 19th Design Automation Conference

January 1982

919 pages

ISBN:0897910206

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IEEE Press

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Published: 01 January 1982

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Shen JAbraham J(1998)Native mode functional test generation for processors with applications to self test and design validationProceedings of the 1998 IEEE International Test Conference10.5555/648020.745609(990-999)Online publication date: 18-Oct-1998
https://dl.acm.org/doi/10.5555/648020.745609
Vandeventer LSantucci JMermet J(1994)Algorithms for behavioral test pattern generation from VHDL circuit descriptions containing loop language constructsProceedings of the conference on European design automation10.5555/198174.198344(638-643)Online publication date: 23-Sep-1994
https://dl.acm.org/doi/10.5555/198174.198344
Vandeventer LSantucci JMermet J(1994)Speeding up test pattern generation from behavioral VHDL descriptions containing several processesProceedings of the conference on European design automation10.5555/198174.198343(632-637)Online publication date: 23-Sep-1994
https://dl.acm.org/doi/10.5555/198174.198343
Santucci JCourbis AGiambiasi NDunlop A(1993)Speed up of behavioral A.T.P.G. using a heuristic criterionProceedings of the 30th international Design Automation Conference10.1145/157485.164587(92-96)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.164587
Bellon CVelazco RZiade H(1988)Analysis of experimental results on functional testing and diagnosis of complex circuitsProceedings of the 1988 international conference on Test: new frontiers in testing10.5555/1896122.1896134(64-72)Online publication date: 12-Sep-1988
https://dl.acm.org/doi/10.5555/1896122.1896134
Shen LSu S(1988)A Functional Testing Method for MicroprocessorsIEEE Transactions on Computers10.1109/12.599237:10(1288-1293)Online publication date: 1-Oct-1988
https://dl.acm.org/doi/10.1109/12.5992
Su SLin TLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)Functional testing techniques for digital LSI/VLSI systemsProceedings of the 21st Design Automation Conference10.5555/800033.800848(517-528)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800848
Su S(1984)IDASProceedings of the July 9-12, 1984, national computer conference and exposition10.1145/1499310.1499329(143-150)Online publication date: 9-Jul-1984
https://dl.acm.org/doi/10.1145/1499310.1499329

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Abstract

References

Cited By

Index Terms

Recommendations

Pseudo-random pattern testing of bridging faults

VLSI testing for high reliability: mixing IDDQ and logic testing

On Complete Functional Broadside Tests for Transition Faults

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