Nothing Special   »   [go: up one dir, main page]

skip to main content
10.1145/764808.764874acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

Using dynamic domino circuits in self-timed systems

Published: 28 April 2003 Publication History

Abstract

We introduce a simple hierarchical design technique for using dynamic domino circuits to build high-performance self-timed data path circuits. We wrap the dynamic domino circuit in a wrapper that communicates using a request/acknowledge protocol and mediates the pre-charge/evaluate cycle of the dynamic logic. We apply standard bundled delay matching for completion detection but add an early completion feature that can signal completion if function validity can be determined from the output value. We call the resulting wrapper semi-bundled because of this early acknowledge. The circuit overhead required for this semi-bundled feature is relatively small, but can provide measurable speedup in some situations. The technique is suitable for any dynamic logic family that has a pre-charge/evaluate cycle, and that produces monotonic output transitions.

References

[1]
Scott Hauck. Asynchronous design methodologies: An overview. Proc. of the IEEE, 83(1):69--93, January 1995.
[2]
Charles L. Seitz. Self-timed VLSI systems. In Charles L. Seitz, editor, Proceedings of the 1st Caltech Conference on Very Large Scale Integration, pages 345--355, Pasadena, CA, January 1979. Caltech C.S. Dept.
[3]
Ivan E. Sutherland. Micropipelines. Communications of the ACM, 32(6):720--738, June 1989.
[4]
Tom Verhoeff. Delay-insensitive codes--an overview. Distributed Computing, 3(1):1--8, 1988.
[5]
Jens Sparsø and Steve Furber, editors. Principles of Asynchronous Circuit Design: A Systems Perspective http://www.wkap.nl/prod/b/0-7923-7613-7. Kluwer Academic Publishers, 2001.
[6]
Erik Brunvand, Steven Nowick, and Kenneth Yun. Practical advances in asynchronous design and in asynchronous-synchronous interfaces. In Proc. ACM/IEEE Design Automation Conference, pages 104--109, 1999.
[7]
Neil Weste and Kamran Eshraghian. Principles of CMOS VLSI Design. Addison-Wesley Publishers, 1993.
[8]
David Chinnery and Kurt Keutzer. Closing the Gap Between ASIC & Custom. Klewer Academic Publishers, 2002.
[9]
Mark E. Dean. STRiP: A Self-Timed RISC Processor Architecture. PhD thesis, Stanford University, 1992.
[10]
S. M. Nowick. Design of a low-latency asynchronous adder using speculative completion. IEE Proceedings, Computers and Digital Techniques, 143(5):301--307, September 1996.
[11]
Kenneth Y. Yun. Automatic synthesis of extended burst-mode circuits using generalized C-elements. In Proc. European Design Automation Conference (EURO-DAC), pages 290--295, September 1996.

Index Terms

  1. Using dynamic domino circuits in self-timed systems

      Recommendations

      Comments

      Please enable JavaScript to view thecomments powered by Disqus.

      Information & Contributors

      Information

      Published In

      cover image ACM Conferences
      GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI
      April 2003
      320 pages
      ISBN:1581136773
      DOI:10.1145/764808
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Sponsors

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 28 April 2003

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. asynchronous circuits
      2. domino logic
      3. self-timed circuits

      Qualifiers

      • Article

      Conference

      GLSVLSI03
      Sponsor:
      GLSVLSI03: Great Lakes Symposium on VLSI 2003
      April 28 - 29, 2003
      D. C., Washington, USA

      Acceptance Rates

      Overall Acceptance Rate 312 of 1,156 submissions, 27%

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • 0
        Total Citations
      • 288
        Total Downloads
      • Downloads (Last 12 months)2
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 21 Sep 2024

      Other Metrics

      Citations

      View Options

      Get Access

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Media

      Figures

      Other

      Tables

      Share

      Share

      Share this Publication link

      Share on social media