Article

A case for dynamic pipeline scaling

Authors:

Jinson Koppanalil,

Prakash Ramrakhyani,

Anu Vaidyanathan,

Eric RotenbergAuthors Info & Claims

CASES '02: Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems

Pages 1 - 8

https://doi.org/10.1145/581630.581632

Published: 08 October 2002 Publication History

Abstract

Energy consumption can be reduced by scaling down frequency when peak performance is not needed. A lower frequency permits slower circuits, and hence a lower supply voltage. Energy reduction comes from voltage reduction, a technique called Dynamic Voltage Scaling (DVS).This paper makes the case that the useful frequency range of DVS is limited because there is a lower bound on voltage. Lowering frequency permits voltage reduction until the lowest voltage is reached. Beyond that point, lowering frequency further does not save energy because voltage is constant.However, there is still opportunity for energy reduction outside the influence of DVS. If frequency is lowered enough, pairs of pipeline stages can be merged to form a shallower pipeline. The shallow pipeline has better instructions-per-cycle (IPC) than the deep pipeline. Since energy also depends on IPC, energy is reduced for a given frequency. Accordingly, we propose Dynamic Pipeline Scaling (DPS). A DPS-enabled deep pipeline can merge adjacent pairs of stages by making the intermediate latches transparent and disabling corresponding feedback paths. Thus, a DPS-enabled pipeline has a deep mode for higher frequencies within the influence of DVS, and a shallow mode for lower frequencies. Shallow mode extends the frequency range for which energy reduction is possible. For frequencies outside the influence of DVS, a DPS-enabled deep pipeline consumes from 23% to 40% less energy than a rigid deep pipeline.

References

[1]

D. H. Albonesi. Dynamic IPC/Clock Rate Optimization. 25th Intel Symp. on Computer Architecture, June 1998.]]

Digital Library

[2]

D. H. Albonesi. Selective Cache Ways: On-Demand Cache Resource Allocation. 32nd Intel Symp. on Microarchitecture, Nov. 1999.]]

Digital Library

[3]

Alpha 21264 Microprocessor Hardware Reference Manual http://ftp.digital.com/pub/Digital/info/semiconductor/literature/21264hrm.pdf]]

[4]

R. Balasubramonian, D. H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures. 33rd Intel Symp. on Microarchitecture, Dec. 2000.]]

Digital Library

[5]

D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. 27th Intel Symp. on Computer Architecture, June 2000.]]

Digital Library

[6]

M. D. Brown, J. Stark, and Y. N. Patt. Select-Free Instruction Scheduling Logic. 34th Intel Symp. on Microarchitecture, Dec. 2001.]]

Digital Library

[7]

K.Bult. Analog Design in Deep Sub-Micron CMOS. 26th European Solid State Circuits Conference, Sep. 2000.]]

[8]

T.D. Burd and R.W. Brodersen. Energy Efficient CMOS Microprocessor Design. Proceedings of the Annual HICSS Conference, Jan. 1995.]]

Digital Library

[9]

D. Burger, T. M. Austin, and S. Bennet. Evaluating Future Microprocessors: The Simplescalar Tool Set. Tech. Rep. CS-TR-96-1308, Univ. Of Wisc.-Madison, July 1996.]]

[10]

A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, and D. H. Albonesi. An Adaptive Issue Queue for Reduced Power at High Performance. Workshop on Power-Aware Computer Systems, Nov. 2000.]]

Digital Library

[11]

A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, and D.H. Albonesi. A Circuit Level Implementation of an Adaptive Issue Queue for Power-Aware Microprocessors. 11th Great Lakes Symposium on VLSI, Mar. 2001.]]

Digital Library

[12]

Crusoe™ Processor Model TM5800 Product Brief http://www.transmeta.com/pdf/specifications/ productbrief_tm5800_05jul01.pdf]]

[13]

Crusoe™ Processor Model TM5400 Product Brief http://www.transmeta.com/technology/specifications/tm5400.html]]

[14]

J. L. Gonzalez, X. Aragones, F. Moll, and A. Rubio. Scaling Trends for Delta Noise in Sub-Micron CMOS Technologies. Design of Integrated Circuits and Systems, Sevilla, Spain, Nov.1996.]]

[15]

J. L. Gonzalez and A. Rubio. Delta-I Noise Scaling in Sub-Micron CMOS Technologies. Workshop on Signal Propagation on Interconnects, Travemunde, Germany, May 1997.]]

[16]

K. Govil, E Chan, and H. Wasserman. Comparing Algorithms for Dynamic Speed-Setting of a Low-Power CPU. 1st Intel Conf. on Mobile Computing and Networking, Nov. 1995.]]

Digital Library

[17]

D. Grunwald, P. Levis, C Morrey III, M. Neufeld, and K. Farkas. Policies for Dynamic Clock Scheduling. Symp. on Operating Systems Design and Implementation, Oct. 2000.]]

Digital Library

[18]

R. Ho, K. W. Mai, and M. A. Horowitz. The Future of Wires. Proceedings of the IEEE, 89(4):490--504, April 2001.]]

[19]

I. Hong, M. Potkonjak, and M. Srivastava. On-line Scheduling of Hard Real-Time Tasks on Variable Voltage Processors. Intel Conf. on Computer-Aided Design, Nov. 1998.]]

Digital Library

[20]

M. S. Hrishikesh, N. Jouppi, K. I. Farkas, D. Burger, S. W. Keckler, and P. Shvakumar. The Optimum Logic Depth Per Pipeline Stage. 29th Intel Symp. on Computer Architecture, May 2002.]]

Digital Library

[21]

D. Kaeli and P. Emma. Branch History Table Prediction of Moving Target Branches due to Subroutine Returns. 18th Intel Symp. on Computer Architecture, May 1991.]]

Digital Library

[22]

Y. Lee and C. Krishna. Voltage Clock Scaling for Low Energy Consumption in Real-Time Embedded Systems. 6th Intel Conf. on Real-Time Computing Systems and Applications, Dec. 1999.]]

Digital Library

[23]

J. Lorch and A. J. Smith. Improving Dynamic Voltage Scaling Algorithms with PACE. Proceedings of the ACM SIGMETRICS 2001 Conf., June 2001.]]

Digital Library

[24]

S. Manne, A. Klauser, and D. Grunwald. Pipeline Gating: Speculation Control for Energy Reduction. 25th Intel Symp. on Computer Architecture, June 1998.]]

Digital Library

[25]

S. McFarling. Combining Branch Predictors. Technical Report WRL-TN-36, Compaq-WRL, June 1993.]]

[26]

T. Pering, T. Burd, and R. Brodersen. The Simulation of Dynamic Voltage Scaling Algorithms. Symposium on Low Power Electronics, Oct. 2000.]]

Digital Library

[27]

M. Weiser, B. Welch, A. Demers, and S. Shenker. Scheduling for Reduced CPU Energy. 1st Symp. on Operating Systems Design and Implementation, Nov. 1994.]]

Digital Library

Cited By

Zhang WZhang HLach J(2021)Extending Performance-Energy Trade-offs Via Dynamic Core ScalingIEEE Transactions on Computers10.1109/TC.2020.302930670:11(1875-1886)Online publication date: 1-Nov-2021
https://doi.org/10.1109/TC.2020.3029306
Gebregiorgis AGolanbari MKiamehr SOboril FTahoori M(2016)Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline OptimizationProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934635(272-277)Online publication date: 8-Aug-2016
https://dl.acm.org/doi/10.1145/2934583.2934635
Chowdhury RKannepalli AKu SRotenberg E(2016)AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS.2016.7482096(214-224)Online publication date: Apr-2016
https://doi.org/10.1109/ISPASS.2016.7482096
Show More Cited By

Index Terms

A case for dynamic pipeline scaling
1. Applied computing
  1. Computers in other domains
    1. Personal computers and PC applications
      1. Microcomputers
2. Computer systems organization

Recommendations

Compiler Support for Dynamic Pipeline Scaling
Embedded and Ubiquitous Computing
Abstract
Low power has played an increasingly important role for embedded systems. To save power, lowering voltage and frequency is very straightforward and effective; therefore dynamic voltage scaling (DVS) has become a prevalent low-power technique. ...
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling

Dynamic voltage scaling (DVS) is a popular approach for energy reduction of integrated circuits. Current processors that use DVS typically have an operating voltage range from full to half of the maximum V_dd. However, there is no fundamental reason why ...
Analysis of energy reduction on dynamic voltage scaling-enabled systems

Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency, based on the computation load, to provide the desired performance with the minimal amount of energy consumption. It has been demonstrated as one of the most ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

CASES '02: Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems

October 2002

324 pages

ISBN:1581135750

DOI:10.1145/581630

General Chairs:
Shuvra S. Bhattacharyya
University of Maryland
,
Trevor Mudge
University of Michigan
,
Program Chairs:
Wayne Wolf
Princeton University
,
Ahmed Jerraya
TIMA, Grenoble, France

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

ACM: Association for Computing Machinery

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 October 2002

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Acceptance Rates

Overall Acceptance Rate 52 of 230 submissions, 23%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

25
Total Citations
View Citations
729
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 20 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Zhang WZhang HLach J(2021)Extending Performance-Energy Trade-offs Via Dynamic Core ScalingIEEE Transactions on Computers10.1109/TC.2020.302930670:11(1875-1886)Online publication date: 1-Nov-2021
https://doi.org/10.1109/TC.2020.3029306
Gebregiorgis AGolanbari MKiamehr SOboril FTahoori M(2016)Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline OptimizationProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934635(272-277)Online publication date: 8-Aug-2016
https://dl.acm.org/doi/10.1145/2934583.2934635
Chowdhury RKannepalli AKu SRotenberg E(2016)AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS.2016.7482096(214-224)Online publication date: Apr-2016
https://doi.org/10.1109/ISPASS.2016.7482096
Saravanan VAnpalagan AWoungang I(2015)An energy-delay product study on chip multi-processors for variable stage pipeliningHuman-centric Computing and Information Sciences10.1186/s13673-015-0046-x5:1Online publication date: 21-Sep-2015
https://doi.org/10.1186/s13673-015-0046-x
Saravanan VAnpalagan AKothari DWoungang IObaidat M(2014)A comparative simulation study on the power---performance of multi-core architectureThe Journal of Supercomputing10.1007/s11227-014-1263-170:1(465-487)Online publication date: 1-Oct-2014
https://dl.acm.org/doi/10.1007/s11227-014-1263-1
Nakabayashi TSasaki TNakamura HOhno KKondo T(2013)Energy Optimization using Fine-Grain Variable Stages Pipeline Processor ChipInternational Journal of Networking and Computing10.15803/ijnc.3.2_1923:2(192-204)Online publication date: 2013
https://doi.org/10.15803/ijnc.3.2_192
Sasaki TNakabayashi TNomura KOhno KKondo T(2013)Design and evaluation of fine‐grain‐mode transition method based on dynamic memory access analysing for variable stages pipeline processorIET Computers & Digital Techniques10.1049/iet-cdt.2012.00677:1(41-47)Online publication date: Jan-2013
https://doi.org/10.1049/iet-cdt.2012.0067
Chang JLee CChen CChang R(2013)Low Power Compiler Optimization for Pipelining ScalingAdvances in Intelligent Systems and Applications - Volume 210.1007/978-3-642-35473-1_63(637-646)Online publication date: 2013
https://doi.org/10.1007/978-3-642-35473-1_63
Nakabayashi TSasaki TOhno KKondo T(2012)Design and evaluation of variable stages pipeline processor with low-energy techniquesIET Computers & Digital Techniques10.1049/iet-cdt.2011.00276:1(43)Online publication date: 2012
https://doi.org/10.1049/iet-cdt.2011.0027
Yao JMiwa SShimada HTomita S(2011)A fine-grained runtime power/performance optimization method for processors with adaptive pipeline depthJournal of Computer Science and Technology10.5555/1991856.199186626:2(292-301)Online publication date: 1-Mar-2011
https://dl.acm.org/doi/10.5555/1991856.1991866
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents