research-article

Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V

Authors:

Pablo Vizcaino,

Georgios Ieronymakis,

Nikolaos Dimou,

Vassilis Papaefstathiou,

Filippo MantovaniAuthors Info & Claims

SC-W '23: Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis

Pages 1543 - 1549

https://doi.org/10.1145/3624062.3624231

Published: 12 November 2023 Publication History

Abstract

For years, SIMD/vector units have enhanced the capabilities of modern CPUs in High-Performance Computing (HPC) and mobile technology. Typical commercially-available SIMD units process up to 8 double-precision elements with one instruction. The optimal vector width and its impact on CPU throughput due to memory latency and bandwidth remain challenging research areas. This study examines the behavior of four computational kernels on a RISC-V core connected to a customizable vector unit, capable of operating up to 256 double precision elements per instruction. The four codes have been purposefully selected to represent non-dense workloads: SpMV, BFS, PageRank, FFT. The experimental setup allows us to measure their performance while varying the vector length, the memory latency, and bandwidth. Our results not only show that larger vector lengths allow for better tolerance of limitations in the memory subsystem but also offer hope to code developers beyond dense linear algebra.

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Cited By

Grima Torres RVizcaíno PMantovani FGutiérrez Moreno J(2024)Co-designing ab initio electronic structure methods on a RISC-V vector architectureOpen Research Europe10.12688/openreseurope.18321.34(165)Online publication date: 14-Nov-2024
https://doi.org/10.12688/openreseurope.18321.3
Grima Torres RVizcaíno PMantovani FGutiérrez Moreno J(2024)Co-designing ab initio electronic structure methods on a RISC-V vector architectureOpen Research Europe10.12688/openreseurope.18321.24(165)Online publication date: 28-Oct-2024
https://doi.org/10.12688/openreseurope.18321.2
Grima Torres RVizcaíno PMantovani FGutiérrez Moreno J(2024)Co-designing ab initio electronic structure methods on a RISC-V vector architectureOpen Research Europe10.12688/openreseurope.18321.14(165)Online publication date: 5-Aug-2024
https://doi.org/10.12688/openreseurope.18321.1
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SC-W '23: Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis

November 2023

2180 pages

ISBN:9798400707858

DOI:10.1145/3624062

Copyright © 2023 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Publication History

Published: 12 November 2023

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European High Performance Computing Joint Undertaking
MCIN/AEI

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SC-W 2023

SC-W 2023: Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis

November 12 - 17, 2023

CO, Denver, USA

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Cited By

Grima Torres RVizcaíno PMantovani FGutiérrez Moreno J(2024)Co-designing ab initio electronic structure methods on a RISC-V vector architectureOpen Research Europe10.12688/openreseurope.18321.34(165)Online publication date: 14-Nov-2024
https://doi.org/10.12688/openreseurope.18321.3
Grima Torres RVizcaíno PMantovani FGutiérrez Moreno J(2024)Co-designing ab initio electronic structure methods on a RISC-V vector architectureOpen Research Europe10.12688/openreseurope.18321.24(165)Online publication date: 28-Oct-2024
https://doi.org/10.12688/openreseurope.18321.2
Grima Torres RVizcaíno PMantovani FGutiérrez Moreno J(2024)Co-designing ab initio electronic structure methods on a RISC-V vector architectureOpen Research Europe10.12688/openreseurope.18321.14(165)Online publication date: 5-Aug-2024
https://doi.org/10.12688/openreseurope.18321.1
Habich DPietrzyk JBarcelo PSanchez-Pi NMeliou ASudarshan S(2024)SIMDified Data Processing - Foundations, Abstraction, and Advanced TechniquesCompanion of the 2024 International Conference on Management of Data10.1145/3626246.3654694(613-621)Online publication date: 9-Jun-2024
https://dl.acm.org/doi/10.1145/3626246.3654694
Perotti MCavalcante MAndri RCavigelli LBenini L(2024)Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source ProcessorIEEE Transactions on Computers10.1109/TC.2024.338889673:7(1822-1836)Online publication date: 15-Apr-2024
https://dl.acm.org/doi/10.1109/TC.2024.3388896
Vizcaino PLabarta JMantovani F(2024)Graph Computing on Long Vector Architectures (Yes, It Works!)2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW63119.2024.00169(986-995)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPSW63119.2024.00169
El Zarif NAskari Hemmat MDupuis TDavid JSavaria Y(2024)Polara-Keras2c: Supporting Vectorized AI Models on RISC-V Edge DevicesIEEE Access10.1109/ACCESS.2024.349846212(171836-171852)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3498462

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