An Efficient ML-based Hardware Trojan Localization Framework for RTL Security Analysis

Recently, the scale of IC designs has been growing rapidly. Due to the popularity of untrusted third-party EDA tools and IP cores, IC designs face the risk of being infected by hardware Trojans (HT), highlighting the increasing importance of EDA for hardware security. RTL designs offer higher flexibility and abstraction level than gate-level netlists, with the potential for faster and more accurate localization of HTs. However, existing HT localization techniques on RTL often exhibit high complexity and low localization resolution, hindering the HT detection and code correction of large-scale applications. To overcome these limitations, we propose an ML-based HT localization framework. We innovatively transform RTL codes into signal transfer graph (STG), reducing the number of digraph nodes by 81%. Additionally, we propose an HT feature description method based on circuit structure and graph centrality, according to which we can achieve signal-level HT localization. Our results show that this method achieves an average of 98% recall, 100% TNR, 99% precision, and 98% F1-measure, outperforming the existing HT localization methods based on RTL analysis.