Nothing Special   »   [go: up one dir, main page]

skip to main content
research-article

IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview

Published: 27 September 2019 Publication History

Abstract

The globalization of the semiconductor supply chain introduces ever-increasing security and privacy risks. Two major concerns are IP theft through reverse engineering and malicious modification of the design. The latter concern in part relies on successful reverse engineering of the design as well. IC camouflaging and logic locking are two of the techniques under research that can thwart reverse engineering by end-users or foundries. However, developing low overhead locking/camouflaging schemes that can resist the ever-evolving state-of-the-art attacks has been a challenge for several years. This article provides a comprehensive review of the state of the art with respect to locking/camouflaging techniques. We start by defining a systematic threat model for these techniques and discuss how various real-world scenarios relate to each threat model. We then discuss the evolution of generic algorithmic attacks under each threat model eventually leading to the strongest existing attacks. The article then systematizes defences and along the way discusses attacks that are more specific to certain kinds of locking/camouflaging. The article then concludes by discussing open problems and future directions.

References

[1]
Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Miaomiao Wang, and Chih-Chao Yang. 2018. Metal finfet anti-fuse. US Patent App. 15/968,235.
[2]
Nail Etkin Can Akkaya, Burak Erbagci, and Ken Mai. 2018. A secure camouflaged logic family using post-manufacturing programming with a 3.6 GHz adder prototype in 65nm CMOS at 1V nominal V DD. In Proceedings of the 2018 IEEE International Solid-State Circuits Conference (ISSCC’18). IEEE, 128--130.
[3]
Yousra Alkabani and Farinaz Koushanfar. 2007. Active hardware metering for intellectual property protection and security. In Proceedings of the USENIX Conference on Security. 291--306.
[4]
Angelos Antonopoulos, Christiana Kapatsori, and Yiorgos Makris. 2017. Security and trust in the analog/mixed-signal/RF domain: A survey and a perspective. In Proceedings of the 2017 22nd IEEE European Test Symposium (ETS’17). IEEE, 1--10.
[5]
Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, and Avesta Sasan. 2019. SMT attack: Next generation attack on obfuscated circuits with capabilities and performance beyond the SAT attacks. IACR Transactions on Cryptographic Hardware and Embedded Systems (2019), 97--122.
[6]
John Backes, Brian Fett, and Marc D. Riedel. 2008. The analysis of cyclic circuits with Boolean satisfiability. In Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design. IEEE Press, 143--148.
[7]
Alex Baumgarten, Akhilesh Tyagi, and Joseph Zambreno. 2010. Preventing IC piracy using reconfigurable logic barriers. IEEE Des. Test Comput. 27, 1 (2010).
[8]
Alex Clark Baumgarten. 2009. Preventing integrated circuit piracy using reconfigurable logic barriers. In IEEE Design and Test of Computers 27, 1 (2010), 66--75.
[9]
Georg T. Becker, Francesco Regazzoni, Christof Paar, and Wayne P. Burleson. 2014. Stealthy dopant-level hardware Trojans: Extended version. J. Cryptogr. Eng. 4, 1 (2014), 19--31.
[10]
J. al Birkner, A. Chan, H. T. Chua, A. Chao, K. Gordon, B. Kleinman, P. Kolze, and R. Wong. 1992. A very-high-speed field-programmable gate array using metal-to-metal antifuse programmable elements. Microelectr. J. 23, 7 (1992), 561--568.
[11]
Abhishek Chakraborty, Yuntao Liu, and Ankur Srivastava. 2018. TimingSAT: Timing profile embedded SAT attack. In Proceedings of the International Conference on Computer-Aided Design. ACM, 6.
[12]
Prabuddha Chakraborty, Jonathan Cruz, and Swarup Bhunia. 2018. SAIL: Machine learning guided structural analysis attack on hardware obfuscation. In Proceedings of the Asian Hardware Oriented Security and Trust Symposium (AsianHOST’18). 56--61.
[13]
R. S. Chakraborty and S. Bhunia. 2009. HARPOON: An obfuscation-based SoC design methodology for hardware protection. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 28, 10 (2009), 1493--1502.
[14]
Rajat Subhra Chakraborty and Swarup Bhunia. 2009. Security against hardware Trojan through a novel application of design obfuscation. In Proceedings of the International Conference on Computer Aided Design. 113--116.
[15]
Shuai Chen, Junlin Chen, Domenic Forte, Jia Di, Mark Tehranipoor, and Lei Wang. 2015. Chip-level anti-reverse engineering using transformable interconnects. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. 109--114.
[16]
Chipworks. 2012. Intel’s 22-nm Tri-gate Transistors Exposed. Retrieved from http://www.eet.bme.hu/ mizsei/Montech/intel-s-22-nm-trigate-transistors-exposed.html.
[17]
Lap-Wai Chow, James P. Baukus, and William M. Clark Jr. 2007. Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide. US Patent 7,294,935.
[18]
Lap-Wai Chow, William M. Clark Jr, and James P. Baukus. 2007. Covert transformation of transistor properties as a circuit protection method. US Patent 7,217,977.
[19]
Ronald P. Cocchi, James P. Baukus, Lap Wai Chow, and Bryan J. Wang. 2014. Circuit camouflage integration for hardware IP protection. In Proceedings of the IEEE/ACM Design Automation Conference. Article 153, 5 pages.
[20]
Ronald P. Cocchi, James P. Baukus, Bryan J. Wang, Lap Wai Chow, and Paul Ouyang. 2012. Building block for a secure CMOS logic cell library. US Patent 8,111,089.
[21]
Jason Cong and Bingjun Xiao. 2014. FPGA-RPI: A novel FPGA architecture with RRAM-based programmable interconnects. IEEE Trans. VLSI Syst. 22, 4 (2014), 864--877.
[22]
Actel Corp. 2002. Design Security in Nonvolatile Flash and Antifuse FPGAs. Actel Corp. Technical Report on QuickLogic FPGAs. Retrieved from http://www.actel.com/documents/DesignSecurity_WP.pdf.
[23]
Franck Courbon, Sergei Skorobogatov, and Christopher Woods. 2016. Reverse engineering flash EEPROM memories using scanning electron microscopy. In Proceedings of the International Conference on Smart Card Research and Advanced Applications. Springer, 57--72.
[24]
Niklas Eén and Niklas Sörensson. 2003. An extensible SAT-solver. In Proceedings of the International Conference on Theory and Applications of Satisfiability Testing. Springer, 502--518.
[25]
Mohamed El Massad, Siddharth Garg, and Mahesh Tripunitara. 2017. Reverse engineering camouflaged sequential circuits without scan access. In Proceedings of the International Conference on Computer Aided Design. IEEE, 33--40.
[26]
Mohamed El Massad, Siddharth Garg, and Mahesh V. Tripunitara. 2015. Integrated circuit (IC) decamouflaging: Reverse engineering camouflaged ICs within minutes. In Proceedings of the Network and Distributed System Security Symposium.
[27]
Burak Erbagci, Cagri Erbagci, Nail Etkin Can Akkaya, and Ken Mai. 2016. A secure camouflaged threshold voltage defined logic family. In Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust. 229--235.
[28]
Marc Fyrbiak, Sebastian Wallat, Jonathan Déchelotte, Nils Albartus, Sinan Böcker, Russell Tessier, and Christof Paar. 2018. On the difficulty of FSM-based hardware obfuscation. IACR Transactions on Cryptographic Hardware and Embedded Systems (2018), 293--330.
[29]
Sanjam Garg, Craig Gentry, Shai Halevi, Mariana Raykova, Amit Sahai, and Brent Waters. 2016. Candidate indistinguishability obfuscation and functional encryption for all circuits. SIAM J. Comput. 45, 3 (2016), 882--929.
[30]
Adria Gascón, Pramod Subramanyan, Bruno Dutertre, Ashish Tiwari, Dejan Jovanović, and Sharad Malik. 2014. Template-based circuit understanding. In Proceedings of the 14th Conference on Formal Methods in Computer-Aided Design. FMCAD Inc, 83--90.
[31]
Jonathan Greene, Sinan Kaptanoglu, Wenyi Feng, Volker Hecht, Joel Landry, Fei Li, Anton Krouglyanskiy, Mihai Morosan, and Val Pevzner. 2011. A 65nm flash-based FPGA fabric optimized for low cost and power. In Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays. ACM, 87--96.
[32]
Ujjwal Guin, Ziqi Zhou, and Adit Singh. 2017. A novel design-for-security (DFS) architecture to prevent unauthorized IC overproduction. In Proceedings of the 2017 IEEE 35th VLSI Test Symposium (VTS’17). IEEE, 1--6.
[33]
Ujjwal Guin, Ziqi Zhou, and Adit Singh. 2018. Robust design-for-security architecture for enabling trust in ic manufacturing and test. IEEE Trans. VLSI Syst. 26, 5 (2018), 818--830.
[34]
Frank Imeson, Ariq Emtenan, Siddharth Garg, and Mahesh Tripunitara. 2013. Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation. In Proceedings of the USENIX Conference on Security. USENIX, 495--510.
[35]
Nithyashankari Gummidipoondi Jayasankaran, Adriana Sanabria Borbon, Edgar Sanchez-Sinencio, Jiang Hu, and Jeyavijayan Rajendran. 2018. Towards provably-secure analog and mixed-signal locking against overproduction. In Proceedings of the International Conference on Computer-Aided Design. ACM, 7.
[36]
Takashi Kono, Tomoya Saito, and Tadaaki Yamauchi. 2018. Overview of embedded flash memory technology. In Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations. Springer, 29--74.
[37]
Farinaz Koushanfar. 2012. Hardware metering: A survey. In Introduction to Hardware Security and Trust. Springer, 103--122.
[38]
Ian Kuon, Russell Tessier, Jonathan Rose, et al. 2008. FPGA architecture: Survey and challenges. Found. Trends Electr. Des. Autom. 2, 2 (2008), 135--253.
[39]
Y. W. Lee and N. A. Touba. 2015. Improving logic obfuscation via logic cone analysis. In Proceedings of the IEEE Latin-American Test Symposium.1--6.
[40]
Leon Li and Alex Orailoglu. 2019. Piercing logic locking keys through redundancy identification. In Design, Automation and Test in Europe Conference 8 Exhibition (DATE'19). 540--545.
[41]
Li Li and Hai Zhou. 2013. Structural transformation for best-possible obfuscation of sequential circuits. In Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust. 55--60.
[42]
Meng Li, Kaveh Shamsi, Yier Jin, and David Z. Pan. 2018. TimingSAT: Decamouflaging timing-based logic obfuscation (unpublished).
[43]
Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, and David Z. Pan. 2016. Provably secure camouflaging strategy for IC protection. In Proceedings of the International Conference on Computer Aided Design. Article 28, 8 pages.
[44]
Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, and David Z. Pan. 2018. A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion. In Proceedings of the Asia and South Pacific Design Automation Conference. 265--270.
[45]
Wenchao Li, A. Gascon, P. Subramanyan, Wei Yang Tan, A. Tiwari, S. Malik, N. Shankar, and S. A. Seshia. 2013. WordRev: Finding word-level structures in a sea of bit-level gates. In Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust. 67--74.
[46]
Timothy Linscott, Pete Ehrett, Valeria Bertacco, and Todd Austin. 2018. SWAN: Mitigating hardware trojans with design ambiguity. In Proceedings of the 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’18). IEEE, 1--7.
[47]
Heiko Lohrke, Shahin Tajik, Christian Boit, and Jean-Pierre Seifert. 2016. No place to hide: Contactless probing of secret data on FPGAs. In Proceedings of the International Conference on Cryptographic Hardware and Embedded Systems. Springer, 147--167.
[48]
Heiko Lohrke, Shahin Tajik, Thilo Krachenfels, Christian Boit, and Jean-Pierre Seifert. 2018. Key extraction using thermal laser stimulation. IACR Transactions on Cryptographic Hardware and Embedded Systems 2018, 3 (Aug. 2018), 573--595.
[49]
S. Malik, G. T. Becker, C. Paar, and W. P. Burleson. 2015. Development of a layout-level hardware obfuscation tool. In Proceedings of the IEEE Annual Symposium on VLSI. 204--209.
[50]
Mohamed El Massad, Siddharth Garg, and Mahesh Tripunitara. 2017. Reverse engineering camouflaged sequential integrated circuits without scan access. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD'17). 33--40.
[51]
Mohamed El Massad, Jun Zhang, Siddharth Garg, and Mahesh V. Tripunitara. 2017. Logic locking for secure outsourced chip fabrication: A new attack and provably secure defense mechanism. arXiv preprint arXiv:1703.10187 (2017).
[52]
Travis Meade, Zheng Zhao, Shaojie Zhang, David Pan, and Yier Jin. 2017. Revisit sequential logic obfuscation: Attacks and defenses. In Proceedings of the IEEE International Symposium on Circuits and Systems. IEEE, 1--4.
[53]
Travis Meade, Zheng Zhao, Shaojie Zhang, David Z. Pan, and Yier Jin. 2017. Revisit sequential logic obfuscation: Attacks and defenses. In Proceedings of the IEEE International Symposium on Circuits and Systems.
[54]
Arlindo L. Oliveira. 2001. Techniques for the creation of digital watermarks in sequential circuit designs. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 20, 9 (2001), 1101--1117.
[55]
Satwik Patnaik, Mohammed Ashra, Johann Knechtel, and Ozgur Sinanoglu. 2017. Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging. In Proceedings of the International Conference on Computer Aided Design. IEEE, 41--48.
[56]
Stephen M. Plaza and Igor L. Markov. 2015. Solving the third-shift problem in IC piracy with test-aware logic locking. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 34, 6 (2015), 961--971.
[57]
Ilia Polian. 2016. Security aspects of analog and mixed-signal circuits. In Proceedings of the 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW’16). IEEE, 1--6.
[58]
Shahed E. Quadir, Junlin Chen, Domenic Forte, Navid Asadizanjani, Sina Shahbazmohamadi, Lei Wang, John Chandy, and Mark Tehranipoor. 2016. A survey on chip to system reverse engineering. ACM J. Emerg. Technol. Comput. Syst. 13, 1 (2016), 6:1--6:34.
[59]
J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri. 2012. Security analysis of logic obfuscation. In Proceedings of the IEEE/ACM Design Automation Conference. 83--89.
[60]
Jeyavijayan Rajendran, Michael Sam, Ozgur Sinanoglu, and Ramesh Karri. 2013. Security analysis of integrated circuit camouflaging. In Proceedings of the ACM Conference on Computer 8 Communications Security. 709--720.
[61]
Jeyavijayan Rajendran, Michael Sam, Ozgur Sinanoglu, and Ramesh Karri. 2013. Security analysis of integrated circuit camouflaging. In Proceedings of the ACM Conference on Computer 8 Communications Security. 709--720.
[62]
Jeyavijayan Rajendran, Huan Zhang, Chi Zhang, Garrett S. Rose, Youngok Pino, Ozgur Sinanoglu, and Ramesh Karri. 2015. Fault analysis-based logic encryption. 64, 2 (2015), 410--424.
[63]
Vaibhav Venugopal Rao and Ioannis Savidis. 2017. Protecting analog circuits with parameter biasing obfuscation. In Proceedings of the 2017 18th IEEE Latin American Test Symposium (LATS’17). IEEE, 1--6.
[64]
Amin Rezaei, You Li, Yuanqi Shen, Shuyu Kong, and Hai Zhou. 2019. CycSAT-unresolvable cyclic logic encryption using unreachable states. In Proceedings of the 24th Asia and South Pacific Design Automation Conference. ACM, 358--363.
[65]
Amin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, and Hai Zhou. 2018. Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks. In Proceedings of the Design, Automation and Test in Europe. IEEE, 85--90.
[66]
Shervin Roshanisefat, Hadi Mardani Kamali, and Avesta Sasan. 2018. SRCLock: SAT-resistant cyclic logic locking for protecting the hardware. arXiv preprint arXiv:1804.09162 (2018).
[67]
Shervin Roshanisefat, Hadi Mardani Kamali, and Avesta Sasan. 2018. SRCLock: SAT-resistant cyclic logic locking for protecting the hardware. In Proceedings of the 2018 on Great Lakes Symposium on VLSI. ACM, 153--158.
[68]
Deepu Roy, Johan H. Klootwijk, Nynke A. M. Verhaegh, Harold H. A. J. Roosen, and Rob A. M. Wolters. 2009. Comb capacitor structures for on-chip physical uncloneable function. IEEE Trans. Semicond. Manufact. 22, 1 (2009), 96--102.
[69]
J. A. Roy, F. Koushanfar, and I. L. Markov. 2008. EPIC: Ending piracy of integrated circuits. In Proceedings of the Conference on Design, Automation and Test in Europe. 1069--1074.
[70]
Abhrajit Sengupta, Mohammed Ashraf, Mohammed Nabeel, and Ozgur Sinanoglu. 2018. Customized locking of IP blocks on a multi-million-gate SoC. In Proceedings of the 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’18). IEEE, 1--7.
[71]
Abhrajit Sengupta, Mohammed Nabeel, Muhammad Yasin, and Ozgur Sinanoglu. 2018. ATPG-based cost-effective, secure logic locking. In Proceedings of the 2018 IEEE 36th VLSI Test Symposium (VTS’18). IEEE, 1--6.
[72]
Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty, and Peter Corcoran. 2017. DSP design protection in CE through algorithmic transformation based structural obfuscation. IEEE Trans. Consum. Electr. 63, 4 (2017), 467--476.
[73]
Bicky Shakya, Haoting Shen, Mark Tehranipoor, and Domenic Forte. 2019. Covert gates: Protecting integrated circuits with undetectable camouflaging. IACR Transactions on Cryptographic Hardware and Embedded Systems 2019, 3 (May 2019), 86--118.
[74]
Bicky Shakya, Mark M. Tehranipoor, Swarup Bhunia, and Domenic Forte. 2017. Introduction to hardware obfuscation: Motivation, methods and evaluation. In Hardware Protection through Obfuscation. Springer, 3--32.
[75]
Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, and Yier Jin. 2017. AppSAT: Approximately deobfuscating integrated circuits. In Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust.
[76]
Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, and Yier Jin. 2017. Circuit obfuscation and oracle-guided attacks: Who can prevail? In Proceedings of the IEEE Great Lakes Symposium on VLSI.
[77]
Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, and Yier Jin. 2017. Cyclic obfuscation for creating SAT-unresolvable circuits. In Proceedings of the IEEE Great Lakes Symposium on VLSI.
[78]
Kaveh Shamsi, Meng Li, David Z. Pan, and Yier Jin. 2018. Cross-lock: Dense layout-level interconnect locking using cross-bar architectures. In Proceedings of the IEEE Great Lakes Symposium on VLSI.
[79]
Kaveh Shamsi, Meng Li, David Z. Pan, and Yier Jin. 2019. KC2: Key-condition crunching for fast sequential circuit deobfuscation. In Proceedings of the 2019 Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE’19). IEEE, 534--539.
[80]
Kaveh Shamsi, Travis Meade, Meng Li, David Z. Pan, and Yier Jin. 2019. On the approximation resiliency of logic locking and IC camouflaging schemes. IEEE Trans. Inf. Forens. Secur. 14, 2 (2019), 347--359.
[81]
Yuanqi Shen, You Li, Shuyu Kong, Amin Rezaei, and Hai Zhou. 2019. SigAttack: New High-level SAT-based Attack on Logic Encryptions. Cryptology ePrint Archive, Report 2019/061. Retrieved from https://eprint.iacr.org/2019/061.
[82]
Yuanqi Shen, You Li, Amin Rezaei, Shuyu Kong, David Dlott, and Hai Zhou. 2019. BeSAT: Behavioral SAT-based attack on cyclic logic encryption. In Proceedings of the 24th Asia and South Pacific Design Automation Conference. ACM, 657--662.
[83]
Yuanqi Shen, Amin Rezaei, and Hai Zhou. 2018. SAT-based bit-flipping attack on logic encryptions. In Proceedings of the Conference on Design, Automation and Test in Europe. IEEE, 629--632.
[84]
Yuanqi Shen and Hai Zhou. 2017. Double DIP: Re-evaluating security of logic encryption algorithms. In Proceedings of the on Great Lakes Symposium on VLSI 2017. ACM, 179--184.
[85]
Mitsuru Shiozaki, Ryohei Hori, and Takeshi Fujino. 2014. Diffusion programmable device: The device to prevent reverse engineering. IACR Cryptology ePrint Archive 2014 (2014), 109.
[86]
Deepak Sirone and Pramod Subramanyan. 2018. Functional analysis attacks on logic locking. arXiv preprint arXiv:1811.12088 (2018).
[87]
Pramod Subramanyan, Sayak Ray, and Sharad Malik. 2015. Evaluating the security of logic encryption algorithms. In Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust. 137--143.
[88]
P. Subramanyan, N. Tsiskaridze, Wenchao Li, A. Gascon, Wei Yang Tan, A. Tiwari, N. Shankar, S. A. Seshia, and S. Malik. 2014. Reverse engineering digital circuits using structural and functional analyses. IEEE Trans. Emerg. Top. Comput. 2, 1 (2014), 63--80.
[89]
Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, and Takeshi Fujino. 2014. Reversing stealthy dopant-level circuits. In Proceedings of the International Conference on Cryptographic Hardware and Embedded Systems. Springer, 112--126.
[90]
Shahin Tajik, Heiko Lohrke, Jean-Pierre Seifert, and Christian Boit. 2017. On the power of optical contactless probing: Attacking bitstream encryption of FPGAs. In Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security. ACM, 1661--1674.
[91]
Randy Torrance and Dick James. 2009. The state-of-the-art in IC reverse engineering. In Proceedings of the International Conference on Cryptographic Hardware and Embedded Systems. Springer, 363--381.
[92]
Pim Tuyls, Geert-Jan Schrijen, Boris Škorić, Jan Van Geloven, Nynke Verhaegh, and Rob Wolters. 2006. Read-proof hardware from protective coatings. In Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems. Springer, 369--383.
[93]
Arunkumar Vijayakumar, Vinay C. Patil, Daniel E. Holcomb, Christof Paar, and Sandip Kundu. 2017. Physical design obfuscation of hardware: A comprehensive investigation of device and logic-level techniques. IEEE Trans. Inf. Forens. Secur. 12, 1 (2017), 64--77.
[94]
Jiafan Wang, Congyin Shi, Adriana Sanabria-Borbon, Edgar Sánchez-Sinencio, and Jiang Hu. 2017. Thwarting analog IC piracy via combinational locking. In Proceedings of the 2017 IEEE International Test Conference (ITC’17). IEEE, 1--10.
[95]
Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, and Gang Qu. 2016. Secure and low-overhead circuit obfuscation technique with multiplexers. In Proceedings of the IEEE Great Lakes Symposium on VLSI. ACM, 133--136.
[96]
Xueyan Wang, Qiang Zhou, Yici Cai, and Gang Qu. 2016. Is the secure IC camouflaging really secure? In Proceedings of the IEEE International Symposium on Circuits and Systems. IEEE, 1710--1713.
[97]
Xueyan Wang, Qiang Zhou, Yici Cai, and Gang Qu. 2018. A conflict-free approach for parallelizing SAT-based de-camouflaging attacks. In Proceedings of the Asia and South Pacific Design Automation Conference. 259--264.
[98]
Xueyan Wang, Qiang Zhou, Yici Cai, and Gang Qu. 2018. Towards a formal and quantitative evaluation framework for circuit obfuscation methods. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. (2018).
[99]
Yang Xie and Ankur Srivastava. 2016. Mitigating SAT attack on logic locking. In Proceedings of the International Conference on Cryptographic Hardware and Embedded Systems. 127--146.
[100]
Yang Xie and Ankur Srivastava. 2017. Delay locking: Security enhancement of logic locking against IC counterfeiting and overproduction. In Proceedings of the IEEE/ACM Design Automation Conference.
[101]
Xiaolin Xu, Bicky Shakya, Mark M. Tehranipoor, and Domenic Forte. 2017. Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks. In Proceedings of the International Conference on Cryptographic Hardware and Embedded Systems. Springer, 189--210.
[102]
Fangfei Yang, Ming Tang, and Ozgur Sinanoglu. 2019. Stripped functionality logic locking with hamming distance based restore unit (SFLL-hd)--Unlocked. IEEE Transactions on Information Forensics and Security (2019).
[103]
Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan Rajendran, and Ozgur Sinanoglu. 2016. SARLock: SAT attack resistant logic locking. In Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust. 236--241.
[104]
Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan J. V. Rajendran, and Ozgur Sinanoglu. 2017. TTLock: Tenacious and traceless logic locking. In Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust. IEEE, 166--166.
[105]
Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, and Jeyavijayan Rajendran. 2016. CamoPerturb: Secure IC camouflaging for minterm protection. In Proceedings of the International Conference on Computer Aided Design. Article 29, 8 pages.
[106]
Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, and Jeyavijayan Rajendran. 2017. Removal attacks on logic locking and camouflaging techniques. IEEE Trans. on Information Forensics and Security (2017).
[107]
Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, and Ozgur Sinanoglu. 2016. Activation of logic encrypted chips: Pre-test or post-test? In Proceedings of the 2016 Conference on Design, Automation 8 Test in Europe. EDA Consortium, 139--144.
[108]
Muhammad Yasin, Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Jeyavijayan J. V. Rajendran, and Ozgur Sinanoglu. 2017. Provably-secure logic locking: From theory to practice. In Proceedings of the ACM Conference on Computer 8 Communications Security. ACM, 1601--1618.
[109]
Muhammad Yasin, Abhrajit Sengupta, Benjamin Carrion Schafer, Yiorgos Makris, Ozgur Sinanoglu, and Jeyavijayan J. V. Rajendran. 2017. What to lock?: Functional and parametric locking. In Proceedings of the IEEE Great Lakes Symposium on VLSI. ACM, 351--356.
[110]
Muhammad Yasin and Ozgur Sinanoglu. 2015. Transforming between logic locking and IC camouflaging. In Proceedings of the 2015 10th International Design 8 Test Symposium (IDT’15). IEEE, 1--4.
[111]
Cunxi Yu, Xiangyu Zhang, Duo Liu, Maciej Ciesielski, and Daniel Holcomb. 2017. Incremental SAT-based reverse engineering of camouflaged logic circuits. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. PP, 99 (2017), 1--1.
[112]
Lin Yuan, Gang Qu, T. Villa, and A. Sangiovanni-Vincentelli. 2008. An FSM reengineering approach to sequential circuit synthesis by state splitting. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 27, 6 (2008), 1159--1164.
[113]
Monir Zaman, Abhrajit Sengupta, Danqing Liu, Ozgur Sinanoglu, Yiorgos Makris, and Jeyavijayan Rajendran. 2018. Towards provably-secure performance locking. In Proceedings of the Conference on Design, Automation and Test in Europe. 1592--1597.
[114]
Li Zhang, Bing Li, Bei Yu, David Z. Pan, and Ulf Schlichtmann. 2018. TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. In Proceedings of the Conference on Design, Automation and Test in Europe.
[115]
Hai Zhou. 2017. A humble theory and application for logic encryption. IACR Cryptology ePrint Archive 2017 (2017), 696.
[116]
Hai Zhou, Ruifeng Jiang, and Shuyu Kong. 2017. CycSAT: SAT-based attack on cyclic logic encryptions. In Proceedings of the International Conference on Computer Aided Design. IEEE, 49--56.
[117]
Hai Zhou, Yuanqi Shen, and Amin Rezaei. 2019. Vulnerability and Remedy of Stripped Function Logic Locking. Cryptology ePrint Archive, Report 2019/139. Retrieved from https://eprint.iacr.org/2019/139.

Cited By

View all
  • (2024)Cybersecurity of autonomous vehicles – threats and mitigationScientific Journal of the Military University of Land Forces10.5604/01.3001.0054.4255211:1(77-96)Online publication date: 31-Mar-2024
  • (2024)Supply Chain Security, Technological Advancements, and Future TrendsSmart and Agile Cybersecurity for IoT and IIoT Environments10.4018/979-8-3693-3451-5.ch010(211-234)Online publication date: 30-Jun-2024
  • (2024)A Module-Level Configuration Methodology for Programmable Camouflaged LogicACM Transactions on Design Automation of Electronic Systems10.1145/364046229:2(1-31)Online publication date: 14-Feb-2024
  • Show More Cited By

Index Terms

  1. IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview

      Recommendations

      Comments

      Please enable JavaScript to view thecomments powered by Disqus.

      Information & Contributors

      Information

      Published In

      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 24, Issue 6
      November 2019
      275 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/3357467
      • Editor:
      • Naehyuck Chang
      Issue’s Table of Contents
      © 2019 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of the United States government. As such, the United States Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Journal Family

      Publication History

      Published: 27 September 2019
      Accepted: 01 June 2019
      Revised: 01 June 2019
      Received: 01 January 2019
      Published in TODAES Volume 24, Issue 6

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. Hardware security
      2. IC camouflaging
      3. logic locking
      4. logic obfuscation

      Qualifiers

      • Research-article
      • Research
      • Refereed

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)143
      • Downloads (Last 6 weeks)17
      Reflects downloads up to 20 Nov 2024

      Other Metrics

      Citations

      Cited By

      View all
      • (2024)Cybersecurity of autonomous vehicles – threats and mitigationScientific Journal of the Military University of Land Forces10.5604/01.3001.0054.4255211:1(77-96)Online publication date: 31-Mar-2024
      • (2024)Supply Chain Security, Technological Advancements, and Future TrendsSmart and Agile Cybersecurity for IoT and IIoT Environments10.4018/979-8-3693-3451-5.ch010(211-234)Online publication date: 30-Jun-2024
      • (2024)A Module-Level Configuration Methodology for Programmable Camouflaged LogicACM Transactions on Design Automation of Electronic Systems10.1145/364046229:2(1-31)Online publication date: 14-Feb-2024
      • (2024)Testing a Transistor-Level Programmable Fabric: Challenges and Solutions2024 IEEE 42nd VLSI Test Symposium (VTS)10.1109/VTS60656.2024.10538901(1-7)Online publication date: 22-Apr-2024
      • (2024)Dual Obfuscation Techniques for DSP Based Circuits2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)10.1109/VLSISATA61709.2024.10560160(1-5)Online publication date: 17-May-2024
      • (2024)IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering AttacksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.333731032:2(347-360)Online publication date: 1-Feb-2024
      • (2024)A Chip-PCB Hybrid SC PUF Used for Anti-Desoldering and Depackaging-Attack ProtectionIEEE Journal of Solid-State Circuits10.1109/JSSC.2024.335204859:7(2330-2344)Online publication date: Jul-2024
      • (2024)Semiconductor supply chain resilience and disruption: insights, mitigation, and future directionsInternational Journal of Production Research10.1080/00207543.2024.2387074(1-24)Online publication date: 13-Aug-2024
      • (2024)Factors influencing the application of forest conservation behavior among rural communities in IranEnvironmental and Sustainability Indicators10.1016/j.indic.2023.10032521(100325)Online publication date: Feb-2024
      • (2024)Influence of resource compensation and complete information on green sustainability of semiconductor supply chainsInternational Journal of Production Economics10.1016/j.ijpe.2024.109227271(109227)Online publication date: May-2024
      • Show More Cited By

      View Options

      Login options

      Full Access

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      HTML Format

      View this article in HTML Format.

      HTML Format

      Media

      Figures

      Other

      Tables

      Share

      Share

      Share this Publication link

      Share on social media