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Weak ordering—a new definition

Authors:

Sarita V. Adve,

Mark D. HillAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 18, Issue 2SI

Pages 2 - 14

https://doi.org/10.1145/325096.325100

Published: 01 May 1990 Publication History

Abstract

A memory model for a shared memory, multiprocessor commonly and often implicitly assumed by programmers is that of sequential consistency. This model guarantees that all memory accesses will appear to execute atomically and in program order. An alternative model, weak ordering, offers greater performance potential. Weak ordering was first defined by Dubois, Scheurich and Briggs in terms of a set of rules for hardware that have to be made visible to software.

The central hypothesis of this work is that programmers prefer to reason about sequentially consistent memory, rather than having to think about weaker memory, or even write buffers. Following this hypothesis, we re-define weak ordering as a contract between software and hardware. By this contract, software agrees to some formally specified constraints, and hardware agrees to appear sequentially consistent to at least the software that obeys those constraints. We illustrate the power of the new definition with a set of software constraints that forbid data races and an implementation for cache-coherent systems that is not allowed by the old definition.

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Index Terms

Weak ordering—a new definition
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Interconnect

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 18, Issue 2SI

Special Issue: Proceedings of the 17th annual international symposium on Computer Architecture

June 1990

356 pages

ISSN:0163-5964

DOI:10.1145/325096

Issue’s Table of Contents

ISCA '90: Proceedings of the 17th annual international symposium on Computer Architecture
May 1990
378 pages
ISBN:0897913663
DOI:10.1145/325164
Chairmen:
Jean-Loup Baer,
Larry Snyder,
James Goodman

Copyright © 1990 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1990

Published in SIGARCH Volume 18, Issue 2SI

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Wang CMohror KSnir M(2024)Formal Definitions and Performance Comparison of Consistency Models for Parallel File SystemsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2024.339105835:6(1092-1106)Online publication date: 18-Apr-2024
https://dl.acm.org/doi/10.1109/TPDS.2024.3391058
Wilkins MWestrick SKandiah VBernat ASuchy BDeiana ECampanoni SAcar UDinda PHardavellas NDubach CBruening DHardekopf B(2023)WARDen: Specializing Cache Coherence for High-Level Parallel LanguagesProceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization10.1145/3579990.3580013(122-135)Online publication date: 17-Feb-2023
https://dl.acm.org/doi/10.1145/3579990.3580013
Peccerillo BCheshmikhani EMannino MMondelli ABartolini S(2023)IXIAM: ISA EXtension for Integrated Accelerator ManagementIEEE Access10.1109/ACCESS.2023.326426511(33768-33791)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3264265
Hirata HNunome A(2023)Performance Evaluation on Parallel Speculation-Based Construction of a Binary Search TreeInternational Journal of Networked and Distributed Computing10.1007/s44227-023-00013-w11:2(88-111)Online publication date: 8-Nov-2023
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Sorin DHill MWood DSorin DHill MWood D(2022)Relaxed Memory ConsistencyA Primer on Memory Consistency and Cache Coherence10.1007/978-3-031-01733-9_5(51-81)Online publication date: 18-Oct-2022
https://doi.org/10.1007/978-3-031-01733-9_5
Li GChen DLu SMusuvathi MNath SSherwood TBerger EKozyrakis C(2021)SherLock: unsupervised synchronization-operation inferenceProceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3445814.3446754(314-328)Online publication date: 19-Apr-2021
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Chou YNg CCattell SIntan JSinclair MDevietti JRogers TAamodt T(2020)Deterministic Atomic Buffering2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00083(981-995)Online publication date: Oct-2020
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Yang SJeong SMin BKim YBurgstaller BBlieberger J(2020)Design-space evaluation for non-blocking synchronization in Ada: lock elision of protected objects, concurrent objects, and low-level atomicsJournal of Systems Architecture10.1016/j.sysarc.2020.101764(101764)Online publication date: Apr-2020
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(2019)ReferencesConcurrency10.1145/3335772.3335940(319-333)Online publication date: 4-Oct-2019
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Merrifield TRoghanchi SDevietti JEriksson JBahar IHerlihy MWitchel ELebeck A(2019)Lazy Determinism for Faster Deterministic MultithreadingProceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3297858.3304047(879-891)Online publication date: 4-Apr-2019
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