- General Chair:
- Iris Bahar
Jointly sponsored by IEEE and ACM, ICCAD is the premier forum to explore emerging technology challenges in electronic design automation, present leading-edge R&D solutions, and identify future roadmaps for design automation research areas.
Proceeding Downloads
A fast thermal-aware fixed-outline floorplanning methodology based on analytical models
Analytical solution of Poisson's equation and its application to VLSI global placement
Novel proximal group ADMM for placement considering fogging and proximity effects
Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems
IC/IP piracy assessment of reversible logic
TimingSAT
Towards provably-secure analog and mixed-signal locking against overproduction
- Nithyashankari Gummidipoondi Jayasankaran,
- Adriana Sanabria Borbon,
- Edgar Sanchez-Sinencio,
- Jiang Hu,
- Jeyavijayan Rajendran
Similar to digital circuits, analog and mixed-signal (AMS) circuits are also susceptible to supply-chain attacks such as piracy, overproduction, and Trojan insertion. However, unlike digital circuits, supply-chain security of AMS circuits is less ...
Best of both worlds
Efficient hardware acceleration of CNNs using logarithmic data representation with arbitrary log-base
NID
AXNet: approximate computing using an end-to-end trainable neural network
Neural network based approximate computing is a universal architecture promising to gain tremendous energy-efficiency for many error resilient applications. To guarantee the approximation quality, existing works deploy two neural networks (NNs), e.g., ...
Scalable-effort ConvNets for multilevel classification
Emerging reconfigurable nanotechnologies
Design and algorithm for clock gating and flip-flop co-optimization
Macro-aware row-style power delivery network design for better routability
Modeling and optimization of magnetic core TSV-inductor for on-chip DC-DC converter
Machine-learning-based dynamic IR drop prediction for ECO
Privacy-preserving deep learning and inference
Machine learning IP protection
Assured deep learning
Tetris
FCN-engine
Designing adaptive neural networks for energy-constrained image classification
FATE
Waterfall is too slow, let's go Agile
Model-based and data-driven approaches for building automation and control
Design automation for battery systems
RFUZZ
Steep coverage-ascent directed test generation for shared-memory verification of multicore chips
SMTSampler
DL-RSIM
A ferroelectric FET based power-efficient architecture for data-intensive computing
- Yun Long,
- Taesik Na,
- Prakshi Rastogi,
- Karthik Rao,
- Asif Islam Khan,
- Sudhakar Yalamanchili,
- Saibal Mukhopadhyay
In this paper, we present a ferroelectric FET (FeFET) based power-efficient architecture to accelerate data-intensive applications such as deep neural networks (DNNs). We propose a cross-cutting solution combining emerging device technologies, circuit ...
EMAT
Co-manage power delivery and consumption for manycore systems using reinforcement learning
Adaptive-precision framework for SGD using deep Q-learning
Differentiated handling of physical scenes and virtual objects for mobile augmented reality
DATC RDF
Physical modeling of bitcell stability in subthreshold SRAMs for leakage-area optimization under PVT variations
Comparing voltage adaptation performance between replica and in-situ timing monitors
Strain-aware performance evaluation and correction for OTFT-based flexible displays
Achieving fast sanitization with zero live data copy for MLC flash memory
Architecting data placement in SSDs for efficient secure deletion implementation
AxBA
Security
Security aspects of neuromorphic MPSoCs
Vulnerability-tolerant secure architectures
Today, secure systems are built by identifying potential vulnerabilities and then adding protections to thwart the associated attacks. Unfortunately, the complexity of today's systems makes it impossible to prove that all attacks are stopped, so clever ...
Machine learning for performance and power modeling of heterogeneous systems
Machine learning for design space exploration and optimization of manycore systems
Failure prediction based on anomaly detection for complex core routers
Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators
Deterministic methods for stochastic computing using low-discrepancy sequences
Design space exploration of multi-output logic function approximations
3DICT
Aliens
FELIX
DNNBuilder
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs
TGPA
Customized locking of IP blocks on a multi-million-gate SoC
Dynamic resource management for heterogeneous many-cores
Online learning for adaptive optimization of heterogeneous SoCs
Hybrid on-chip communication architectures for heterogeneous manycore systems
A practical detailed placement algorithm under multi-cell spacing constraints
Mixed-cell-height placement considering drain-to-drain abutment
Mixed-cell-height legalization considering technology and region constraints
Mixed-cell-height placement with complex minimum-implant-area constraints
RAPID
Sneak path free reconfiguration of via-switch crossbars based FPGA
Mixed size crossbar based RRAM CNN accelerator with overlapped mapping method
Enhancing the solution quality of hardware ising-model solver via parallel tempering
Defensive dropout for hardening deep neural networks under adversarial attacks
Online human activity recognition using low-power wearable devices
Shadow attacks on MEDA biochips
LeapChain
Robust object estimation using generative-discriminative inference for secure robotics applications
Efficient utilization of adversarial training towards robust machine learners and its analysis
Majority logic synthesis
RouteNet
TritonRoute
A multithreaded initial detailed routing algorithm considering global routing guides
Extending ML-OARSMT to net open locator with efficient and effective boolean operations
Logic synthesis of binarized neural networks for efficient circuit implementation
Canonicalization of threshold logic representation and its applications
DALS
Unlocking fine-grain parallelism for AIG rewriting
High-level synthesis with timing-sensitive information flow enforcement
Specialized hardware accelerators are being increasingly integrated into today's computer systems to achieve improved performance and energy efficiency. However, the resulting variety and complexity make it challenging to ensure the security of these ...
Property specific information flow analysis for hardware security verification
HISA
SWAN
Security for safety
Hardware-accelerated data acquisition and authentication for high-speed video streams on future heterogeneous automotive processing platforms
Network and system level security in connected vehicle applications
A safety and security architecture for reducing accidents in intelligent transportation systems
The need and opportunities of electromigration-aware integrated circuit design
Uncertainty quantification of electronic and photonic ICs with non-Gaussian correlated process variations
Since the invention of generalized polynomial chaos in 2002, uncertainty quantification has impacted many engineering fields, including variation-aware design automation of integrated circuits and integrated photonics. Due to the fast convergence rate, ...
Parallelizable Bayesian optimization for analog and mixed-signal rare failure detection with high coverage
Transient circuit simulation for differential algebraic systems using matrix exponential
CustomTopo
A cross-layer methodology for design and optimization of networks in 2.5D systems
Wavefront-MCTS
HLS-based optimization and design space exploration for applications with variable loop bounds
HLSPredict: cross platform performance prediction for FPGA high-level synthesis
FPGA application developers must explore increasingly large design spaces to identify regions of code to accelerate. High-Level Synthesis (HLS) tools automatically derive FPGA-based designs from high-level language specifications, which improves ...
C-GOOD
LiteHAX
SCADET
Industrial experiences with resource management under software randomization in ARINC653 avionics environments
Single flux quantum circuit technology and CAD overview
Design automation methodology and tools for superconductive electronics
Josephson junction-based superconducting logic families have been proposed to implement analog and digital signals, which can achieve low energy dissipation and ultra-fast switching speed. There are two representative technologies: DC-biased RSFQ (rapid ...
Multi-terminal routing with length-matching for rapid single flux quantum circuits
Electromagnetic equalizer
GPU acceleration of RSA is vulnerable to side-channel timing attacks
Remote inter-chip power analysis side-channel attacks at board-level
Effective simple-power analysis attacks of elliptic curve cryptography on embedded systems
SODA
PolySA
An efficient data reuse strategy for multi-pattern data access
Optimizing data layout and system configuration on FPGA-based heterogeneous platforms
Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion
Area-efficient and low-power face-to-face-bonded 3D liquid state machine design
DIMA
Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips
Multi-physics-based FEM analysis for post-voiding analysis of electromigration failure effects
Estimating and optimizing BTI aging effects
PVT2
Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML
Computer-aided design for quantum computation
PolyCleaner
A formal instruction-level GPU model for scalable verification
Fast FPGA emulation of analog dynamics in digitally-driven systems
SPN dash
Watermarking deep neural networks for embedded systems
DeepFense
Enabling deep learning at the IoT edge
Searching toward pareto-optimal device-aware neural architectures
- An-Chieh Cheng,
- Jin-Dong Dong,
- Chi-Hung Hsu,
- Shu-Huan Chang,
- Min Sun,
- Shih-Chieh Chang,
- Jia-Yu Pan,
- Yu-Ting Chen,
- Wei Wei,
- Da-Cheng Juan
Recent breakthroughs in Neural Architectural Search (NAS) have achieved state-of-the-art performance in many tasks such as image classification and language understanding. However, most existing works only optimize for model accuracy and largely ignore ...
Hardware-aware machine learning
Index Terms
- Proceedings of the International Conference on Computer-Aided Design