- Conference Chair:
- Toshio Endo,
- General Chairs:
- Mitsuo Yokokawa,
- Toshihiro Hanawa,
- Program Chair:
- Osamu Tatebe
High performance computing (HPC) is, today, a key technology to solve large problems in science, engineering, and business by utilizing tremendous computing power which has been evolving to the future. HPC Asia, which is an international conference series on HPC technologies in Asia Pacific region, and was held in the past several times in several countries in Asia regional sites to discuss the issues on high performance computing and to exchange information of research and development results in HPC.
Proceeding Downloads
Performance evaluation for a hydrodynamics application in XcalableACC PGAS language for accelerated clusters
Clusters equipped with accelerators such as GPUs and MICs are used widely. To use these clusters, programmers write programs for their applications by combining MPI with one of the accelerator programming models such as CUDA and OpenACC. The accelerator ...
Investigating the performance and productivity of DASH using the Cowichan problems
DASH is a new realization of the PGAS (Partitioned Global Address Space) programming model in the form of a C++ template library. Instead of using a custom compiler, DASH provides expressive programming constructs using C++ abstraction mechanisms and ...
Recent experiences in using MPI-3 RMA in the DASH PGAS runtime
The Partitioned Global Address Space (PGAS) programming model has become a viable alternative to traditional message passing using MPI. The DASH project provides a PGAS abstraction entirely based on C++11. The underlying DASH RunTime, DART, provides ...
Towards a parallel algebraic multigrid solver using PGAS
The Algebraic Multigrid (AMG) method has over the years developed into an efficient tool for solving unstructured linear systems. The need to solve large industrial problems discretized on unstructured meshes, has been a key motivation for devising a ...
Linkage of XcalableMP and Python languages for high productivity on HPC cluster system: application to graph order/degree problem
When developing applications on high-performance computing (HPC) cluster systems, Partitioned Global Address Space (PGAS) languages are used due to their high productivity and performance. However, in order to more efficiently develop such applications, ...
Optimizing two-electron repulsion integral calculation on knights landing architecture
In this paper, we introduced some optimization methods we used to optimize two-electron repulsion integral calculation on Knights Landing architecture. We developed a schedule for parallelism and vectorization, and we compared two different methods for ...
Performance evaluation for omni XcalableMP compiler on many-core cluster system based on knights landing
To reduce the programming cost on a cluster system, Partitioned Global Address Space (PGAS) languages are used. We have designed an XcalableMP (XMP) PGAS language and developed the Omni XMP compiler (Omni compiler) for XMP. In the present study, we ...
Scaling collectives on large clusters using Intel(R) architecture processors and fabric
- Masashi Horikoshi,
- Larry Meadows,
- Tom Elken,
- Pradeep Sivakumar,
- Edward Mascarenhas,
- James Erwin,
- Dmitry Durnov,
- Alexander Sannikov,
- Toshihiro Hanawa,
- Taisuke Boku
This paper provides results on scaling Barrier and Allreduce to 8192 nodes on a cluster of Intel® Xeon Phi™ processors installed at the University of Tokyo and the University of Tsukuba. We will describe the effects of OS and platform noise on the ...
OpenMP-based parallel implementation of matrix-matrix multiplication on the intel knights landing
The second generation Intel Xeon Phi processor codenamed Knights Landing (KNL) have emerged with 2D tile mesh architecture. Implementing of the general matrix-matrix multiplication on a new architecture is an important practice. To date, there has not ...
Multiple endpoints for improved MPI performance on a lattice QCD code
This paper provides results using multiple threads and a high-performance MPI implementation of MPI_THREAD_MULTIPLE applied to a Lattice QCD Code (CCS-QCD) and run on the Oakforest-PACS machine. Performance has improved from the baseline code by as much ...
Optimizing a particle-in-cell code on Intel knights landing
The particle-in-cell (PIC) code is one of the mainstream algorithms in the laser plasma research area. However, the programming challenges to achieve high performance of PIC codes on the Intel Knights Landing (KNL) processor is widely concerned by global ...
Index Terms
- Proceedings of Workshops of HPC Asia
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SIGGRAPH Asia
Asia is rising. While Japan has been dominant economically for decades, China and India are growing at a phenomenal rate, and the four Asian tigers, Hong Kong, Korea, Singapore and Taiwan are still strongly on the prowl. Asian governments are pumping ...
HPC Asia is reborn
After a ten-year hiatus, HPC Asia took place in January 2018 in Tokyo, Japan. HPC Asia is a SIGHPC in-cooperation event. We asked the steering committee chair, Taisuke Boku (University of Tsukba), to give us a brief history of HPC Asia and summary of ...
HPC Ecosystems Project: Facilitating Advanced Research Computing in Africa
PEARC '19: Practice and Experience in Advanced Research Computing 2019: Rise of the Machines (learning)This poster will describe the HPC Ecosystems Project, a primary responsibility of South Africa's Centre for High Performance Computing (CHPC), which targets HPC deployment and Advanced Research Computing capacity development within the borders of South ...
Acceptance Rates
| Year | Submitted | Accepted | Rate |
|---|---|---|---|
| HPCAsia '23 | 34 | 15 | 44% |
| HPCAsia '23 Workshops | 10 | 9 | 90% |
| HPCAsia '19 | 32 | 15 | 47% |
| HPCAsia '18 | 67 | 30 | 45% |
| Overall | 143 | 69 | 48% |