research-article

Vectorization of Multibyte Floating Point Data Formats

Authors:

Andrew Anderson,

David GreggAuthors Info & Claims

PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation

Pages 363 - 372

https://doi.org/10.1145/2967938.2967966

Published: 11 September 2016 Publication History

Abstract

We propose a scheme for reduced-precision representation of floating point data on a continuum between IEEE-754 floating point types. Our scheme enables the use of lower precision formats for a reduction in storage space requirements and data transfer volume. We describe how our scheme can accelerated using existing hardware vector units on a general-purpose processor (GPP). Exploiting native vector hardware allows us to support reduced precision floating point with low overhead. We demonstrate that supporting reduced precision in the compiler as opposed to using a library approach can yield a low overhead solution for GPPs.

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Cited By

Mukunoki DKawai MImamura T(2023)Sparse Matrix-Vector Multiplication with Reduced-Precision Memory Accessor2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)10.1109/MCSoC60832.2023.00094(608-615)Online publication date: 18-Dec-2023
https://doi.org/10.1109/MCSoC60832.2023.00094
Jost TDurand YFabre CCohen APétrot FLee J(2021)Seamless compiler integration of variable precision floating-point arithmeticProceedings of the 2021 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO51591.2021.9370331(65-76)Online publication date: 27-Feb-2021
https://dl.acm.org/doi/10.1109/CGO51591.2021.9370331
Anderson AMuralidharan SGregg D(2017)Efficient Multibyte Floating Point Data Formats Using VectorizationIEEE Transactions on Computers10.1109/TC.2017.271635566:12(2081-2096)Online publication date: 1-Dec-2017
https://doi.org/10.1109/TC.2017.2716355
Show More Cited By

Index Terms

Vectorization of Multibyte Floating Point Data Formats

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Information

Published In

cover image ACM Conferences

PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation

September 2016

474 pages

ISBN:9781450341219

DOI:10.1145/2967938

General Chairs:
Ayal Zaks
Intel, Israel
,
Bilha Mendelson
Optitura, Israel
,
Program Chairs:
Lawrence Rauchwerger
Texas A&M University, USA
,
Wen-mei W. Hwu
University of Illinois at Urbana-Champaign, USA

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IFIP WG 10.3: IFIP WG 10.3
IEEE TCCA: IEEE Computer Society Technical Committee on Computer Architecture
SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE CS TCPP: IEEE Computer Society Technical Committee on Parallel Processing

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 September 2016

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Science Foundation Ireland

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PACT '16

Sponsor:

IFIP WG 10.3
IEEE TCCA
SIGARCH
IEEE CS TCPP

PACT '16: International Conference on Parallel Architectures and Compilation

September 11 - 15, 2016

Haifa, Israel

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PACT '16 Paper Acceptance Rate 31 of 119 submissions, 26%;

Overall Acceptance Rate 121 of 471 submissions, 26%

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Cited By

Mukunoki DKawai MImamura T(2023)Sparse Matrix-Vector Multiplication with Reduced-Precision Memory Accessor2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)10.1109/MCSoC60832.2023.00094(608-615)Online publication date: 18-Dec-2023
https://doi.org/10.1109/MCSoC60832.2023.00094
Jost TDurand YFabre CCohen APétrot FLee J(2021)Seamless compiler integration of variable precision floating-point arithmeticProceedings of the 2021 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO51591.2021.9370331(65-76)Online publication date: 27-Feb-2021
https://dl.acm.org/doi/10.1109/CGO51591.2021.9370331
Anderson AMuralidharan SGregg D(2017)Efficient Multibyte Floating Point Data Formats Using VectorizationIEEE Transactions on Computers10.1109/TC.2017.271635566:12(2081-2096)Online publication date: 1-Dec-2017
https://doi.org/10.1109/TC.2017.2716355
Mukunoki DImamura T(2016)Reduced-Precision Floating-Point Formats on GPUs for High Performance and Energy Efficient Computation2016 IEEE International Conference on Cluster Computing (CLUSTER)10.1109/CLUSTER.2016.77(144-145)Online publication date: Sep-2016
https://doi.org/10.1109/CLUSTER.2016.77

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