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Early-Stage Power Grid Design: Extraction, Modeling and Optimization

Published: 01 June 2014 Publication History

Abstract

Many prior works have discussed the power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the early stage of a development cycle, designers have more flexibility to improve the design quality. However, there are several fundamental challenges at early-stage when design database is NOT complete, including extraction, modeling and optimization. This paper tackles these fundamental issues of early-stage power grid design. The proposed methods have been silicon-validated on 32nm on-market chips and successfully applied to a 22nm design for its early stage power grid design. The findings from such practices reveal that, for sub-32nm chips, intrinsic on-die capacitance and power gate scheme may have more significant impact than expected on power integrity, and need to be well addressed at early stage.

References

[1]
A. Dharchoudhury, et. al., "Design and analysis of power distribution networks in PowerPC#8482; microprocessors," in Proc. DAC, 1998, pp. 738--743.
[2]
R. Panda, et. al., "Model and analysis for combined package and on-chip power grid simulation", in Proc. ISLPED, 2000, pp. 179--284.
[3]
K. Arabi, et. al., "Power Supply Noise in SoCs: Metrics, Management, and Measurement," IEEE D & T, vol. 24(3): 236--244, 2007.
[4]
S. Lin, et. al., "Full-chip vectorless dynamic PI analysis and verification against 100uV/100ps-resolution measurement," in Proc. CICC, pp. 509--512, 2004.
[5]
E. Chiprout, "Fast flip-chip power grid analysis via locality and grid shells", in Proc. ICCAD, 2004, pp. 485--488.
[6]
Y. Shi and L. He, "Modeling and design for beyond-the-die power integrity," in Proc. ICCAD, 2010, pp. 411--416.
[7]
H. Zheng, et. al., "On-package decoupling optimization with package macromodels," in Proc. CICC, 2003, pp. 723--726.
[8]
J. Zhao, et. al., "Effects of power/ground via distribution on the power/ground performance of C4/BGA packages," in Proc. EPEP, 1998, pp. 177--180.
[9]
T. H. Chen and C. C.-P. Chen, "Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods," in Proc. DAC, 2001, pp. 559--562.
[10]
H. Qian, et. al., "Power Grid Analysis Using Random Walks," IEEE Trans. CAD, vol. 24 (8): 1204--1224, 2005.
[11]
J. Kozhaya, et. al., "A Multigrid-Like Technique for Power Grid Analysis," IEEE Trans. CAD, vol. 21(10): 1148--1160, 2002.
[12]
C. Zhuo, et. al., "Power Grid Analysis and Optimization Using Algebraic Multigrid," IEEE Trans. CAD, vol. 27(4): 738--751, 2009.
[13]
Z. Feng and P. Li, "Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms," in Proc. ICCAD, 2008, pp. 647--654.
[14]
Q. He, et. al., "From Layout Directly to Simulation: A First-Principle Guided Circuit Simulator of Linear Complexity and Its Efficient Parallelization," IEEE Trans. CPMT, vol. 2(4): 687--699, 2012.
[15]
X.-D. S. Tan and C.-J. R. Shi, "Fast power/ground network optimization based on equivalent circuit modeling," in Proc. DAC, 2001, pp. 550--554.
[16]
H. Qian, et. al., "Early-Stage Power Grid Analysis for Uncertain Working Modes," IEEE Trans. CAD, vol. 24(5): 676--682, 2005.
[17]
N. Ghani, et. al. "Fast vectorless power grid verification using an approximate inverse technique," in Proc. DAC, 2005, pp. 184--189.
[18]
C. Zhuo, et. al., "A silicon-validated methodology for power delivery modeling and simulation," in Proc. ICCAD, 2012, pp. 255--262.
[19]
W. Kao, et. al., "Parasitic Extraction: Current State of the Art and Future Trends," Proc. of IEEE, vol. 89: 729--739, 2001.
[20]
K. Mattan, et. al., "Interconnect parasitic extraction in the digital IC design methodology," in Proc. ICCAD, 1999, pp. 223--230.
[21]
Y. Le Coz and R. Iverson, "A Stochastic Algorithm for High Speed Capacitance Extraction in Integrated Circuits," Solid-State Electronics, vol.35 (7): 1005--1012, 1992.
[22]
Y. Le Coz and J. Jere, "An Improved Floating-Random-Walk Algorithm for Solving the Multi-Dielectric Dirichlet Problem", IEEE Trans. MTT, vol. 41 (2): 325--329, 1993
[23]
A. Husain, "Models for interconnect capacitance extraction", in Proc. ISQED, 2001, pp. 167--172.
[24]
Y. Liu, et. al., "Correlation of On-Die capacitance for power delivery network," in Proc. EPEP, 2008, pp. 123--126.
[25]
Y. Jiang, and K. Cheng, "Vector Generation for Power Supply Noise Estimation and Verification of Deep Submicron Designs," IEEE Trans. VLSI, vol. 9(2): 329--340, 2001.
[26]
J. Phillips and L. Silveira, "Poorman's TBR: a simple model reduction scheme," in Proc. DATE, 2004, pp. 938--943.
[27]
L. Lee, et. al., "HiPRIME: Hierarchical and Passivity Preserved Interconnect Macromodeling Engine for RLKC Power Delivery," IEEE Trans. CAD, vol. 24(5): 797--806, 2005.
[28]
G. Antonini, "SPICE Equivalent Circuits of Frequency Domain Responses," IEEE Trans. EC, vol. 45(3): 502--512, 2003.
[29]
H. Jiang, et. al., "Benefits and costs of power-gating technique," in Proc. ICCD, 2005, pp. 559--566.
[30]
C. Long and L. He, "Distributed Sleep Transistor Network for Power Reduction," IEEE Trans. VLSI, vol. 12(9): 937--946, 2004.
[31]
H. Jiang and M. Marek-Sadowska, "Power gating scheduling for power/ground noise reduction," in Proc. DAC 2008, pp. 980--985.

Cited By

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  • (2019)From Layout to System: Early Stage Power Delivery and Architecture Co-ExplorationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283443838:7(1291-1304)Online publication date: Jul-2019
  • (2017)Accelerating chip design with machine learning: From pre-silicon to post-silicon2017 30th IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2017.8226046(227-232)Online publication date: Sep-2017
  • (2016)A novel cross-layer framework for early-stage power delivery and architecture co-explorationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897969(1-6)Online publication date: 5-Jun-2016
  • Show More Cited By
  1. Early-Stage Power Grid Design: Extraction, Modeling and Optimization

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    cover image ACM Other conferences
    DAC '14: Proceedings of the 51st Annual Design Automation Conference
    June 2014
    1249 pages
    ISBN:9781450327305
    DOI:10.1145/2593069
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 01 June 2014

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    View all
    • (2019)From Layout to System: Early Stage Power Delivery and Architecture Co-ExplorationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283443838:7(1291-1304)Online publication date: Jul-2019
    • (2017)Accelerating chip design with machine learning: From pre-silicon to post-silicon2017 30th IEEE International System-on-Chip Conference (SOCC)10.1109/SOCC.2017.8226046(227-232)Online publication date: Sep-2017
    • (2016)A novel cross-layer framework for early-stage power delivery and architecture co-explorationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897969(1-6)Online publication date: 5-Jun-2016
    • (2016)Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.252390835:10(1681-1694)Online publication date: 1-Oct-2016
    • (2015)A Cross-Layer Approach for Early-Stage Power Grid Design and OptimizationACM Journal on Emerging Technologies in Computing Systems10.1145/270024612:3(1-20)Online publication date: 21-Sep-2015

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