research-article

An improved benchmark suite for the ISPD-2013 discrete cell sizing contest

Authors:

Muhammet Mustafa Ozdal,

Cheng ZhuoAuthors Info & Claims

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

Pages 168 - 170

https://doi.org/10.1145/2451916.2451959

Published: 24 March 2013 Publication History

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Abstract

Gate sizing and threshold voltage selection is an important step in the VLSI design process to optimize power and performance of a given netlist. In this paper, we provide an overview of the ISPD-2013 Discrete Cell Sizing Contest. Compared to the ISPD-2012 Contest, we propose improvements in terms of the benchmark suite and the timing models utilized. In this paper, we briefly describe the contest, and provide some details about the standard cell library, benchmark suite, timing infrastructure and the evaluation metrics.

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Cited By

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Ye YChen TWang ZYan HYu BShi L(2024)Fast and Accurate Aging-Aware Cell Timing Model via Graph LearningIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.329891771:1(156-160)Online publication date: Jan-2024
https://doi.org/10.1109/TCSII.2023.3298917
Jain ADas PAcharyya AMB R(2024)ANN-based Accurate and Fast Post-Route QoR Data Prediction Methodology from Pre-Clock Tree Synthesis by Skipping CTS and Routing2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10557874(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10557874
Mangiras DChinnery DDimitrakopoulos G(2023)Task-Based Parallel Programming for Gate SizingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319749042:4(1309-1322)Online publication date: Apr-2023
https://doi.org/10.1109/TCAD.2022.3197490
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Index Terms

An improved benchmark suite for the ISPD-2013 discrete cell sizing contest
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Hardware validation

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Information & Contributors

Information

Published In

ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

March 2013

194 pages

ISBN:9781450319546

DOI:10.1145/2451916

General Chair:
Cheng-Kok Koh
Purdue University
,
Program Chair:
Cliff Sze
IBM Research

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 March 2013

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Research-article

Conference

ISPD'13

Sponsor:

SIGDA

ISPD'13: International Symposium on Physical Design

March 24 - 27, 2013

Nevada, Stateline, USA

Acceptance Rates

Overall Acceptance Rate 62 of 172 submissions, 36%

Upcoming Conference

ISPD '25

Sponsor:
sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

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Cited By

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Ye YChen TWang ZYan HYu BShi L(2024)Fast and Accurate Aging-Aware Cell Timing Model via Graph LearningIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.329891771:1(156-160)Online publication date: Jan-2024
https://doi.org/10.1109/TCSII.2023.3298917
Jain ADas PAcharyya AMB R(2024)ANN-based Accurate and Fast Post-Route QoR Data Prediction Methodology from Pre-Clock Tree Synthesis by Skipping CTS and Routing2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10557874(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10557874
Mangiras DChinnery DDimitrakopoulos G(2023)Task-Based Parallel Programming for Gate SizingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319749042:4(1309-1322)Online publication date: Apr-2023
https://doi.org/10.1109/TCAD.2022.3197490
Wang ZGuo ZShi X(2023)A Variation-Aware Lagrangian Relaxation-Based Gate Sizing Framework for Timing Optimization2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218448(309-313)Online publication date: 8-May-2023
https://doi.org/10.1109/ISEDA59274.2023.10218448
Chinnery DSharma ABehjat LYang S(2022)Integrating LR Gate Sizing in an Industrial Place-and-Route FlowProceedings of the 2022 International Symposium on Physical Design10.1145/3505170.3511480(39-48)Online publication date: 13-Apr-2022
https://dl.acm.org/doi/10.1145/3505170.3511480
Tziantzioulis GChang TBalkind JTu JGao FWentzlaff D(2022)OPDB: A Scalable and Modular Design BenchmarkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309679441:6(1878-1887)Online publication date: Jun-2022
https://doi.org/10.1109/TCAD.2021.3096794
Li BLin R(2022)Scalable Synthetic Circuit Generation using Geometry Embedding for CAD Tool Assessment2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937638(3239-3243)Online publication date: 28-May-2022
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Mangiras DDimitrakopoulos G(2021)Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage AssignmentTechnologies10.3390/technologies90400929:4(92)Online publication date: 26-Nov-2021
https://doi.org/10.3390/technologies9040092
Pentapati SKu BLim SLienig JBehjat LYang S(2021)ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip OptimizationProceedings of the 2021 International Symposium on Physical Design10.1145/3439706.3447266(75-82)Online publication date: 22-Mar-2021
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Stefanidis AMangiras DNicopoulos CChinnery DDimitrakopoulos G(2021)Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.302554140:8(1672-1686)Online publication date: Aug-2021
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