Article

Free access

Boosting the performance of hybrid snooping cache protocols

Author:

Fredrik DahlgrenAuthors Info & Claims

ISCA '95: Proceedings of the 22nd annual international symposium on Computer architecture

Pages 60 - 69

https://doi.org/10.1145/223982.223998

Published: 01 May 1995 Publication History

Abstract

Previous studies of bus-based shared-memory multiprocessors have shown hybrid write-invalidate/write-update snooping protocols to be incapable of providing consistent performance improvements over write-invalidate protocols. In this paper, we analyze the deficiencies of hybrid snooping protocols under release consistency, and show how these deficiencies can be dramatically reduced by using write caches and read snarfing.Our performance evaluation is based on program-driven simulation and a set of five scientific applications with different sharing behaviors including migratory sharing as well us producer-consumer sharing. We show that a hybrid protocol, extended with write caches as well as read snarfing, manages to reduce the number of coherence misses by between 83% and 95% as compared to a write-invalidate protocol for all five applications in this study. In addition, the number of bus transactions is reduced by between 36% and 60% for four of the applications and by 9% for the fifth application. Because of the small implementation cost of the hybrid protocol and the two extensions, we believe that this combination is an effective approach to boost the performance of bus-based multiprocessors.

References

[1]

Anderson, C. and Baer, J.-L. "Two Techniques tbr Improving Performance on Bus-Based Multiprocessors," in Proc. of the 1st Int. Symposium on l-ligh-Pe~ormance Computer Architecture, pp.256-275, 1995.

Digital Library

[2]

Archibald, J.K. "A Cache Coherence Approach For Large Multiprocessor Systems," in Proc. of the 1988 international Conference on Supercomputing, pp.337-345, 1988.

Digital Library

[3]

Brorsson, M., Dahlgren, E, Nilsson, H., and Stenstrrm, P. "The CacheMire Test Bench -- A Flexible and Effective Approach for Simulation of Multiprocessors," in Proc. of the 26th Annual Simulation Symposium, pp. 41-49, 1993.

[4]

Dahlgren, E and Stenstrrm, P. "Using Write Caches to Improve Performance of Cache Coherence Protocols in Shared-Memory Multiprocessors," in Journal oJ Parallel and Distributed Computing, Vol. 26, No 2, April I995.

Digital Library

[5]

DEC, "DECChip 21064 - A RISC Microproces,~~or Preliminary Data Sheet," Digital Equipment Corporation, Maynard, Massachusetts, 1993.

[6]

Eggers, S.J. and Katz, R.H. "A Characterization of Sharing in Parallel Programs and its Application to Coherency Protocol Evaluation," in Proc. of the 15th Ann. Int. Symposium on Computer Architecture, pp.373-382, 1988.

Digital Library

[7]

Eggers, S.J. and Katz, R.H. "Evaluating the l?erformance of Four Snooping Cache Coherence Protocols," in Proc. of the 16th Annual International Symposium on Computer Architecture, pp.2-15, 1989.

Digital Library

[8]

Galles, M. and Williams, E. "Performance optimizations, Implementation, and Verification of the SGI Challenge Multiprooessor," in Proc. of the 27th Hawaii Int. Conference on System Sciences, Vol. 1, pp.134-143, 1994.

[9]

Gharachorloo K., Gupta A., Hennessy J. "Performance Evaluation of Memory Consistency Models for Shared-Memory Multiprocessors," in Proc. of ASPLOS IV, pp.245-257, 1991.

Digital Library

[10]

Goodman, J.R. and Woest, P.J. "The Wisconsin Multicube: A New Large-Scale Cache-Coherent Multiprocessor," in Pvoc. of the 15th Ann. Int. Symposium on Computer Architecture, pp.422-431, I988.

Digital Library

[11]

Jouppi, N.P. "Cache Write Policies and Performance," In Proc. of the 20th Annual International Sympostum on Computer Architecture, pp. 191- 201, I993.

Digital Library

[12]

Karlin, M.R., Manasse, M.S., Rudolph, L., and Sleator, D.D. "Competitive Snoopy Caching," in Proc. oJ the 27th Annual Symposium on Foundations oj Computer Science, pp.244-254, 1986.

[13]

Papamarcos, M. and Patel, J. "A Low Overhead Coherence Solution for Multiprocessors with Private Cache Memories," in Proc. of the llth Ann. Int. Symposium on Computer Architecture, pp.348-354, 1984.

Digital Library

[14]

Rudolph, L. and Segall, Z. "Dynamic Decentralized Cache Schemes for MIMD Parallel Processors," in Proc. of the 11th Ann. Int. Symposium on Computer Architecture, pp.340-347, 1984.

Digital Library

[15]

Singh, J.P., Weber, W.-D., and Gupta, A. "SPLASH: Stanford Parallel Applications for Shared-Memory," in Computer Architecture News, 20(1):5-44, March 1992.

Digital Library

[16]

Thacker, C.P., Conroy, L.C., and Stewart, L.C. "The Alpha Demonstration Unit: A High-Performance Multiprocessor for Software and Chip Development," in Digital Technical Journal, 4(4):51-65, 1992.

[17]

Thacker, C.P. and Stewart, L.C. "Firefly: A Multiprocessor Workstation," in Proc. of ASPLOS II, pp.164-172, 1987.

[18]

Veenstra, J.E. and Fowler, R.J. "The Prospect.~ for On-Line Hybrid Coherency Protocols on Bus-Based Multtprocessor.,g'. Tech. Report No. 490. Comp. Systems Department, University of Rochester, March 1994.

Digital Library

Cited By

Chirkov GWentzlaff DGallivan KNikolopoulos DBeivide RGallopoulos E(2023)Seizing the Bandwidth Scaling of On-Package Interconnect in a Post-Moore's Law WorldProceedings of the 37th International Conference on Supercomputing10.1145/3577193.3593702(410-422)Online publication date: 21-Jun-2023
https://dl.acm.org/doi/10.1145/3577193.3593702
Franques AKokolis AAbadal SFernando VMisailovic STorrellas J(2021)WiDir: A Wireless-Enabled Directory Cache Coherence Protocol2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00034(304-317)Online publication date: Feb-2021
https://doi.org/10.1109/HPCA51647.2021.00034
Kayi ASerres OEl-Ghazawi T(2015)Adaptive Cache Coherence Mechanisms with Producer–Consumer Sharing Optimization for Chip MultiprocessorsIEEE Transactions on Computers10.1109/TC.2013.21764:2(316-328)Online publication date: 1-Feb-2015
https://dl.acm.org/doi/10.1109/TC.2013.217
Show More Cited By

Index Terms

Boosting the performance of hybrid snooping cache protocols

Recommendations

Techniques for Improving Performance of Hybrid Snooping Cache Protocols

Bus-based multiprocessors constitute a cost-effective class of shared-memory multiprocessors. Private caches are the key to an efficient utilization of the shared bus, and most such systems use a write-invalidate cache-coherence protocol to keep the ...
Evaluating the performance of four snooping cache coherency protocols
Special Issue: Proceedings of the 16th annual international symposium on Computer Architecture

Write-invalidate and write-broadcast coherency protocols have been criticized for being unable to achieve good bus performance across all cache configurations. In particular, write-invalidate performance can suffer as block size increases; and large ...
Boosting the performance of hybrid snooping cache protocols
Special Issue: Proceedings of the 22nd annual international symposium on Computer architecture (ISCA '95)

Previous studies of bus-based shared-memory multiprocessors have shown hybrid write-invalidate/write-update snooping protocols to be incapable of providing consistent performance improvements over write-invalidate protocols. In this paper, we analyze ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

ISCA '95: Proceedings of the 22nd annual international symposium on Computer architecture

July 1995

426 pages

ISBN:0897916980

DOI:10.1145/223982

Chairman:
David A. Patterson
Univ. of California, Berkeley

ACM SIGARCH Computer Architecture News Volume 23, Issue 2
Special Issue: Proceedings of the 22nd annual international symposium on Computer architecture (ISCA '95)
May 1995
412 pages
ISSN:0163-5964
DOI:10.1145/225830
Chairman:
David A. Patterson
Univ. of California, Berkeley
Issue’s Table of Contents

Copyright © 1995 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS\TCCA: TC on Computer Arhitecture

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1995

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ISCA95

Sponsor:

SIGARCH
IEEE-CS\TCCA

ISCA95: International Conference on Computer Architecture

June 22 - 24, 1995

S. Margherita Ligure, Italy

Acceptance Rates

Overall Acceptance Rate 543 of 3,203 submissions, 17%

Upcoming Conference

ISCA '25

Sponsor:
sigarch

The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

26
Total Citations
View Citations
569
Total Downloads

Downloads (Last 12 months)76
Downloads (Last 6 weeks)13

Reflects downloads up to 28 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Chirkov GWentzlaff DGallivan KNikolopoulos DBeivide RGallopoulos E(2023)Seizing the Bandwidth Scaling of On-Package Interconnect in a Post-Moore's Law WorldProceedings of the 37th International Conference on Supercomputing10.1145/3577193.3593702(410-422)Online publication date: 21-Jun-2023
https://dl.acm.org/doi/10.1145/3577193.3593702
Franques AKokolis AAbadal SFernando VMisailovic STorrellas J(2021)WiDir: A Wireless-Enabled Directory Cache Coherence Protocol2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00034(304-317)Online publication date: Feb-2021
https://doi.org/10.1109/HPCA51647.2021.00034
Kayi ASerres OEl-Ghazawi T(2015)Adaptive Cache Coherence Mechanisms with Producer–Consumer Sharing Optimization for Chip MultiprocessorsIEEE Transactions on Computers10.1109/TC.2013.21764:2(316-328)Online publication date: 1-Feb-2015
https://dl.acm.org/doi/10.1109/TC.2013.217
Kayi ASerres OEl-Ghazawi T(2014)Bandwidth Adaptive Cache Coherence Optimizations for Chip MultiprocessorsInternational Journal of Parallel Programming10.1007/s10766-013-0247-842:3(435-455)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1007/s10766-013-0247-8
Latif KSeceleanu TSeceleanu CTenhunen H(2011)Service based communication for MPSoC platform-SegBusMicroprocessors & Microsystems10.1016/j.micpro.2011.06.00635:7(643-655)Online publication date: 1-Oct-2011
https://dl.acm.org/doi/10.1016/j.micpro.2011.06.006
Kayi AEl-Ghazawi TEl-Shishiny HRohou E(2010)An adaptive cache coherence protocol for chip multiprocessorsProceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies10.1145/1882453.1882458(1-10)Online publication date: 19-Jun-2010
https://dl.acm.org/doi/10.1145/1882453.1882458
Latif KTenhunen HSeceleanu T(2009)MultiCast protocol for SegBus platform2009 NORCHIP10.1109/NORCHP.2009.5397854(1-6)Online publication date: Nov-2009
https://doi.org/10.1109/NORCHP.2009.5397854
Huh JChang JBurger DSohi G(2004)Coherence decouplingACM SIGOPS Operating Systems Review10.1145/1037949.102440638:5(97-106)Online publication date: 7-Oct-2004
https://dl.acm.org/doi/10.1145/1037949.1024406
Huh JChang JBurger DSohi G(2004)Coherence decouplingACM SIGARCH Computer Architecture News10.1145/1037947.102440632:5(97-106)Online publication date: 7-Oct-2004
https://dl.acm.org/doi/10.1145/1037947.1024406
Huh JChang JBurger DSohi G(2004)Coherence decouplingACM SIGPLAN Notices10.1145/1037187.102440639:11(97-106)Online publication date: 7-Oct-2004
https://dl.acm.org/doi/10.1145/1037187.1024406
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents