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A distributed algorithm for layout geometry operations

Published: 05 June 2011 Publication History

Abstract

This paper introduces a novel distributed algorithm for performing layout geometry operations usually found in design rule checking, layout verification and/or mask synthesis. Typically, during the mask synthesis flow, a large number of machines are available to the user. Also, as multiple machines/cores become more ubiquitous, even designers using layout verification tools will have access to a large set of machines. Having an efficient and scalable distributed algorithm for performing sequences of layout geometry operations will be of great value to both the designer and the mask synthesis engineer.
This paper seeks to present such an algorithm. Given a layout and a sequence of layout geometry operations, the layout is divided into several partitions. The given sequence of layout geometry operations is executed in parallel on the different partitions. The partitions are merged in a systematic manner and the sequence of operations is repeated on a suitable set of polygons in these newly derived partitions until a partition that covers the entire layout area is obtained. A key feature of the proposed algorithm is that it is correct-by-construction - i.e., each partition is guaranteed to generate a subset of the correct results. The complete and correct results are generated for each layout geometry operation for the entire layout when the operation completes execution on all the partitions. Results on large industrial layouts are very promising and show good performance and scalability.

References

[1]
Gearman. http://gearman.org/.
[2]
Caliber user's manual.
[3]
Hercules user's manual.
[4]
S. Koranne. A High Performance SIMD Framework for Design Rule Checking on Sony's PlayStation 2 Emotion Engine Platform, In IEEE International Symposium on Quality Electronic Design, Pages 371--376, 2004.
[5]
K. MacPherson and P. Banerjee. Parallel Algorithms for VLSI Layout Verification, In Journal of Parallel and Distributed Computing, Vol. 36, Issue 2, Pages 156--172, 1996.
[6]
Y. Wang. Verifying an IC layout in individual regions and combining results, United States Patent Publication - Pub No. US 2006/0265675 A1, 2006.

Cited By

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  • (2023)Invited Paper: Heterogeneous Acceleration for Design Rule Checking2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323957(1-7)Online publication date: 28-Oct-2023
  • (2023)OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247734(1-6)Online publication date: 9-Jul-2023

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  1. A distributed algorithm for layout geometry operations

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    cover image ACM Conferences
    DAC '11: Proceedings of the 48th Design Automation Conference
    June 2011
    1055 pages
    ISBN:9781450306362
    DOI:10.1145/2024724
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 05 June 2011

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    Author Tags

    1. design rule checking
    2. parallel processing

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    • (2023)Invited Paper: Heterogeneous Acceleration for Design Rule Checking2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323957(1-7)Online publication date: 28-Oct-2023
    • (2023)OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247734(1-6)Online publication date: 9-Jul-2023

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