research-article

A case for neuromorphic ISAs

Authors:

James Jamal Thomas,

Mikko LipastiAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 39, Issue 1

Pages 145 - 158

https://doi.org/10.1145/1961295.1950385

Published: 05 March 2011 Publication History

Abstract

The desire to create novel computing systems, paired with recent advances in neuroscientific understanding of the brain, has led researchers to develop neuromorphic architectures that emulate the brain. To date, such models are developed, trained, and deployed on the same substrate. However, excessive co-dependence between the substrate and the algorithm prevents portability, or at the very least requires reconstructing and retraining the model whenever the substrate changes. This paper proposes a well-defined abstraction layer -- the Neuromorphic instruction set architecture, or NISA -- that separates a neural application's algorithmic specification from the underlying execution substrate, and describes the Aivo framework, which demonstrates the concrete advantages of such an abstraction layer. Aivo consists of a NISA implementation for a rate-encoded neuromorphic system based on the cortical column abstraction, a state-of-the-art integrated development and runtime environment (IDE), and various profile-based optimization tools. Aivo's IDE generates code for emulating cortical networks on the host CPU, multiple GPGPUs, or as boolean functions. Its runtime system can deploy and adaptively optimize cortical networks in a manner similar to conventional just-in-time compilers in managed runtime systems (e.g. Java, C#).

We demonstrate the abilities of the NISA abstraction by constructing a cortical network model of the mammalian visual cortex, deploying on multiple execution substrates, and utilizing the various optimization tools we have created. For this hierarchical configuration, Aivo's profiling based network optimization tools reduce the memory footprint by 50% and improve the execution time by a factor of 3x on the host CPU. Deploying the same network on a single GPGPU results in a 30x speedup. We further demonstrate that a speedup of 480x can be achieved by deploying a massively scaled cortical network across three GPGPUs. Finally, converting a trained hierarchical network to C/C++ boolean constructs on the host CPU results in 44x speedup.

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Index Terms

A case for neuromorphic ISAs
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing
2. Hardware
  1. Communication hardware, interfaces and storage

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 39, Issue 1

ASPLOS '11

March 2011

407 pages

ISSN:0163-5964

DOI:10.1145/1961295

Issue’s Table of Contents

ASPLOS XVI: Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
March 2011
432 pages
ISBN:9781450302661
DOI:10.1145/1950365
General Chair:
Rajiv Gupta
University of California, Riverside
,
Program Chair:
Todd C. Mowry
Carnegie Mellon University

Copyright © 2011 ACM.

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Published: 05 March 2011

Published in SIGARCH Volume 39, Issue 1

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https://doi.org/10.1038/s41586-020-2782-y
Hajj NAwad M(2019)A piecewise weight update rule for a supervised training of cortical algorithmsNeural Computing and Applications10.1007/s00521-017-3167-531:6(1915-1930)Online publication date: 20-Jul-2019
https://dl.acm.org/doi/10.1007/s00521-017-3167-5
Hajj NAwad M(2017)A biologically inspired deep neural network of basal ganglia switching in working memory tasks2017 IEEE Symposium Series on Computational Intelligence (SSCI)10.1109/SSCI.2017.8285364(1-8)Online publication date: Nov-2017
https://doi.org/10.1109/SSCI.2017.8285364
Hajj NFilo MAwad M(2017)Automated composer recognition for multi-voice piano compositions using rhythmic features, n-grams and modified cortical algorithmsComplex & Intelligent Systems10.1007/s40747-017-0052-x4:1(55-65)Online publication date: 8-Aug-2017
https://doi.org/10.1007/s40747-017-0052-x
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Chen YLan HDu ZLiu STao JHan DLuo TGuo QLi LXie YChen T(2019)An Instruction Set Architecture for Machine LearningACM Transactions on Computer Systems10.1145/333146936:3(1-35)Online publication date: 13-Aug-2019
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Riera MArnau JGonzález A(2018)Computation reuse in DNNs by exploiting input similarityProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00016(57-68)Online publication date: 2-Jun-2018
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