research-article

Forwardflow: a scalable core for power-constrained CMPs

Authors:

David A. WoodAuthors Info & Claims

ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture

Pages 14 - 25

https://doi.org/10.1145/1815961.1815966

Published: 19 June 2010 Publication History

Abstract

Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased core-per-socket count will continue, despite a lack of parallel software to exercise the hardware. Future CMPs must deliver thread-level parallelism when software provides threads to run, but must also continue to deliver performance gains for single threads by exploiting instruction-level parallelism and memory-level parallelism. However, power limitations will prevent conventional cores from exploiting both simultaneously.

This work presents the Forwardflow Architecture, which can scale its execution logic up to run single threads, or down to run multiple threads in a CMP. Forwardflow dynamically builds an explicit internal dataflow representation from a conventional instruction set architecture, using forward dependence pointers to guide instruction wakeup, selection, and issue. Forwardflow's backend is organized into discrete units that can be individually (de-)activated, allowing each core's performance to be scaled by system software at the architectural level.

On single threads, Forwardflow core scaling yields a mean runtime reduction of 21% for a 37% increase in power consumption. For multithreaded workloads, a Forwardflow-based CMP allows system software to select the performance point that best matches available power.

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Attia KEl-Hosseini MAli H(2017)Dynamic power management techniques in multi-core architectures: A survey studyAin Shams Engineering Journal10.1016/j.asej.2015.08.0108:3(445-456)Online publication date: Sep-2017
https://doi.org/10.1016/j.asej.2015.08.010
SHIOYA RTAKAMI RGOSHIMA MANDO H(2016)FXA: Executing Instructions in Front-End for Energy EfficiencyIEICE Transactions on Information and Systems10.1587/transinf.2015EDP7316E99.D:4(1092-1107)Online publication date: 2016
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Index Terms

Forwardflow: a scalable core for power-constrained CMPs
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
      2. Self-organizing autonomic computing

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cover image ACM Conferences

ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture

June 2010

520 pages

ISBN:9781450300537

DOI:10.1145/1815961

General Chair:
André Seznec
INRIA Rennes
,
Program Chairs:
Uri Weiser
Technion
,
Ronny Ronen
Intel

ACM SIGARCH Computer Architecture News Volume 38, Issue 3
ISCA '10
June 2010
508 pages
ISSN:0163-5964
DOI:10.1145/1816038
Issue’s Table of Contents

Copyright © 2010 ACM.

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Published: 19 June 2010

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Cited By

Zhou YYu ZZhang CXu YWang HWang SSun NBao YZhou HMoreira JMueller FEtsion Y(2021)OmegaflowProceedings of the 35th ACM International Conference on Supercomputing10.1145/3447818.3460367(152-163)Online publication date: 3-Jun-2021
https://dl.acm.org/doi/10.1145/3447818.3460367
Attia KEl-Hosseini MAli H(2017)Dynamic power management techniques in multi-core architectures: A survey studyAin Shams Engineering Journal10.1016/j.asej.2015.08.0108:3(445-456)Online publication date: Sep-2017
https://doi.org/10.1016/j.asej.2015.08.010
SHIOYA RTAKAMI RGOSHIMA MANDO H(2016)FXA: Executing Instructions in Front-End for Energy EfficiencyIEICE Transactions on Information and Systems10.1587/transinf.2015EDP7316E99.D:4(1092-1107)Online publication date: 2016
https://doi.org/10.1587/transinf.2015EDP7316
Nowatzki TGangadhar VSankaralingam K(2016)A Heterogeneous Von Neumann/Explicit Dataflow ProcessorIEEE Micro10.1109/MM.2016.3436:3(20-30)Online publication date: May-2016
https://doi.org/10.1109/MM.2016.34
Nowatzki TGangadhar VSankaralingam K(2015)Exploring the potential of heterogeneous von neumann/dataflow execution modelsACM SIGARCH Computer Architecture News10.1145/2872887.275038043:3S(298-310)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2872887.2750380
Nowatzki TGangadhar VSankaralingam KMarr DAlbonesi D(2015)Exploring the potential of heterogeneous von neumann/dataflow execution modelsProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750380(298-310)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2749469.2750380
Jha SHeirman WFalcón ACarlson TVan Craeynest KTubella JGonzález AEeckhout LNapoli CSalapura VFranke HHou R(2015)ChryssoProceedings of the 12th ACM International Conference on Computing Frontiers10.1145/2742854.2742885(1-8)Online publication date: 6-May-2015
https://dl.acm.org/doi/10.1145/2742854.2742885
Shioya RGoshima MAndo HFlautner KWenisch TOzer EFerdman M(2014)A Front-end Execution Architecture for High Energy EfficiencyProceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2014.35(419-431)Online publication date: 13-Dec-2014
https://dl.acm.org/doi/10.1109/MICRO.2014.35
Buono DMencagli GPascucci AVanneschi M(2014)Performance analysis and structured parallelisation of the space–time adaptive processing computational kernel on multi-core architecturesInternational Journal of Parallel, Emergent and Distributed Systems10.1080/17445760.2014.88596729:5(460-498)Online publication date: 11-Feb-2014
https://doi.org/10.1080/17445760.2014.885967
Petrica PIzraelevitz AAlbonesi DShoemaker C(2013)FlickerACM SIGARCH Computer Architecture News10.1145/2508148.248592441:3(13-23)Online publication date: 23-Jun-2013
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