DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only)
Authors: 
Yangyang Pan, Tong ZhangAuthors Info & Claims
Page 290
Abstract
Motivated by the emerging three-dimensional (3D integration technologies, this paper studies the potential of applying 3D memory stacking to enable FPGA devices use on-chip DRAM cells to store configuration data. In current design practice, FPGAs do not use on-chip DRAM cells for configuration data storage mainly because on-chip DRAM self-refreshing involves destructive DRAM read operations. This problem can be solved if we use a 3D stacked memory as primary FPGA configuration data storage and externally refresh on-chip DRAM cells. Since the 3D stacked memory can easily store multiple sets of configuration data, it can meanwhile enable high-speed FPGA dynamic reconfiguration. In this paper, we study such DRAM-based FPGA design enabled by 3D memory stacking and investigate potential design issues, and employ the VPR tool set to demonstrate that DRAM-based FPGAs can noticeably reduce FPGA die area and hence improve speed and energy consumption performance, compared their SRAM-based counterparts.
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February 2010
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Published: 21 February 2010
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